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ASME Press Select Proceedings
International Conference on Mechanical and Electrical Technology, 3rd, (ICMET-China 2011), Volumes 1–3
Yi Xie
Yi Xie
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ASME Press
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The multi-level cache hierarchy has long been adopted in microprocessors to deal with the memory wall problem. Nevertheless, contention misses and data thrashing in the shared LLC may still hurt performance due to interference between multiple threads running on the same processor. Based on application's temporal reuse behavior, we propose a Reuse Frequency based Filter (RFF) algorithm to select possible reused data from replaced data, reducing harmful displacement of useful data and data thrashing of the shared LLC on a chip Multi-Processor (CMP) architecture. Our simulation results show that the proposed mechanism can effectively reduce harmful replacements and cache conflicts by 19.7% and increase IPC of programs by 1.68% on average.

Key Words
I. Introduction
2. Related Research
3. RFF
4. Performance Evaluation and Analysis
5. Conclusion
6. Acknowledgment
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