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ASME Press Select Proceedings
International Conference on Computer Technology and Development, 3rd (ICCTD 2011)
Jianhong Zhou
Jianhong Zhou
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ASME Press
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This paper proposed a novel half-pixel interpolation implementation scheme of H.264/AVC based on the resource of C64x+ DSP (Digital signal processor) and characteristic of cache on TMS320C64x+ platform. Firstly, the theory of H.264 half-pixel interpolation was analyzed. Then half-pixel horizontal interpolation process was optimized with a parallel computing pattern. For further reducing the cache miss rate and cache bank conflicts, Half-pixel vertical interpolation process was equally transformed to matrix transposition and horizontal interpolation process. Finally, the optimized scheme were realized by linear assembly language, Simulation results show that the optimized scheme was effective and could result in 3.5 times speed accelerating. In addition, there was no performance loss during the optimized scheme process.

Key Words
I Introduction
II. Half-Pixel Interpolation in H.264/AVC
III. Half-Pixel Interpolation Optimization
IV. Experimental Results
V. Summaries
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