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ASME Press Select Proceedings

International Conference on Computer Technology and Development, 3rd (ICCTD 2011)

By
Jianhong Zhou
Jianhong Zhou
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ISBN:
9780791859919
No. of Pages:
2000
Publisher:
ASME Press
Publication date:
2011

A high speed data processing system has been designed based on NIOS II reconfigurable soft IP cores. The mainly task of the system is to process data at high speed meanwhile to ensure the correctness of data. In this condition, user-defined SRAM logic controller combine complex flash operate mode has been designed to deal with plenty of data at high speed take the advantage of the reconfigurable characteristic of soft IP cores. System signal bit is 16, update speed is 10MHz and signal enable period is 15.3ms. SRAM using pingpang change structure processing data. By generating SRAM hardware interrupt changing Avalon bus control right and adding user-defined information such as head, time stamp ,data length and so on to ensure the correctness of data. System resource usage condition and power consumption also mentioned in detail. Wideband input voltage designed adapted to remote system control requirement. Through long time use, system has high reliability and stability.

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