International Conference on Instrumentation, Measurement, Circuits and Systems (ICIMCS 2011)
283 Cache Insertion Policy Based on Each Thread's Behavior
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The last-level cache (LLC) mitigates the long latencies of memory access in today's chip multi-core processor (CMP). The insertion policy in the LLC largely affects cache efficiency, and an inappropriate insertion policy may lead useless blocks to be remained in the cache longer than necessary, resulting in inefficiency. Currently commonly used insertion policies are unaware of each thread's behavior of the simultaneously running threads in the CMP. Threads which constantly re-reference cache block with a long time always behave worse than threads with short time re-reference behavior. In this paper, we propose an insertion policy that based on each thread's...