Skip to Main Content
Skip Nav Destination
ASME Press Select Proceedings
International Conference on Instrumentation, Measurement, Circuits and Systems (ICIMCS 2011)Available to Purchase
By
Chen Ming
Chen Ming
Search for other works by this author on:
ISBN:
9780791859902
No. of Pages:
1400
Publisher:
ASME Press
Publication date:
2011

The last-level cache (LLC) mitigates the long latencies of memory access in today's chip multi-core processor (CMP). The insertion policy in the LLC largely affects cache efficiency, and an inappropriate insertion policy may lead useless blocks to be remained in the cache longer than necessary, resulting in inefficiency. Currently commonly used insertion policies are unaware of each thread's behavior of the simultaneously running threads in the CMP. Threads which constantly re-reference cache block with a long time always behave worse than threads with short time re-reference behavior. In this paper, we propose an insertion policy that based on each thread's behavior (ETB) of the simultaneously running threads in the CMP. Such technique requires minor hardware modification over the least-recently-used (LRU) replacement policy. Our evaluation shows that our ETB improves IPCsum by 1.95%, Weighted Speedup by 1.86% and IPCnorm_hmean by 2.55% on average over LRU insertion policy, and 3.49%, 2.67%, 2.64% respectively over MRU insertion policy.

Abstract
Keywords:
Introduction
Backround & Related Work
Insertion Policy Based on Each Thread's Behavior
Experimental Setup
Results & Analysis
Conclusion
Acknowledgments
References
This content is only available via PDF.
You do not currently have access to this chapter.

or Create an Account

Close Modal
Close Modal