International Conference on Instrumentation, Measurement, Circuits and Systems (ICIMCS 2011)
252 Facing the Challenges of Designing an Ethernet Network Interfaces for 100 GBPS
Download citation file:
- Ris (Zotero)
- Reference Manager
Designing and implementation of high-performance Network Interfaces (NI) for servers become very challenging. Especially after the communication line speed exceeds the 10 Gbps. In this paper, we proposes a new ENI model that support the Large Segment Offload (LSO) for sending side and a novel technique called Receiving Side Amalgamating (RSA) for receiving side and which is used for incoming packets. The core engine assigned to handle these functions is single specialized embedded processors utilizing RISC cores in each side. As a result, a 240 MHz RISC core can be used in Ethernet Network Interface ENI card for wide range of transmission line speed up to 100 Gbps. These results are based on the use of a specialized RISC core that we developed and simulated.