81 A Novel 4-bits 10GS/s ADC Combining Time-Interleaved and Double-Sampling Techniques

A novel 4-bits 10GS/s ADC is presented in the paper The ADC combines the time-interleaved and double-sampling techniques for the first time. Because of the use of double-sampling technique, the ADC needs only the half of the clocks of the traditional time-interleaved ADC. The design of the ADC in 180nm CMOS process technology is described in detail in the paper. The stimulation results show that the SFDR of the ADC achieves 37.68dB at 10GS/s.