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ASME Press Select Proceedings

International Conference on Information Technology and Computer Science, 3rd (ITCS 2011)

Editor
V. E. Muhin
V. E. Muhin
National Technical University of Ukraine
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W. B. Hu
W. B. Hu
Wuhan University
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ISBN:
9780791859742
No. of Pages:
656
Publisher:
ASME Press
Publication date:
2011

At present, secure chips are playing an important role in network and information security. However, the widely used secure chips at home and abroad, are mostly dedicated to a specific algorithm, such as MD5, SHA-1 and so on. It is difficult for a dedicated secure chip to meet various users' needs at multiple levels of security, for its algorithm is fixed and not changeable. This paper first analyzed the basic procedures of the most popular SHA algorithms such as SHA-1, SHA-256, SHA-384 and SHA-512. Then, the SHA algorithms using Verilog HDL were implemented in the Quartus II IDE. Finally, using reconfigurable architecture and reusable design idea, we present the reconfigurable modules and units in the detailed implementations, and propose a reconfigurable secure chip design method implementing the four SHA algorithms. The results show that the reconfigurable SHA secure chip based on the Altera's Cyclone FPGA can flexibly implement different algorithms, achieve full utilization of resources, save a large number of logic resources, and overcome the shortcomings of traditional implementations.

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