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International Conference on Computer Engineering and Technology, 3rd (ICCET 2011)

Jianhong Zhou
Jianhong Zhou
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Scaling and power reduction trends in present technology causes sub threshold leakage currents to become an increasingly large component of total power dissipation. This paper presents Multi-threshold voltage technique for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. Here 1-bit CMOS full adder taken as an example and implemented using MTCMOS technology and compared for the power and delay parameters using Cadence Virtuoso UMC 0.18µm. Further layout and RC parametric extraction has also been done using physical verification tool.

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