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International Conference on Optimization Design (ICOD 2010)

Xingkuan Wu
Xingkuan Wu
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Li Yu
Li Yu
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ASME Press
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With the development of process technologies and increased complexity of chips, SoC (System-on-Chip) testing becomes more and more difficult. Traditional testing methods cannot meet the current design requirements anymore. In this paper, we present a DFT (design-for-testability) scheme for an industrial application SoC chip basing on SMIC 130nm CMOS technology, it includes boundary scan test, memory BIST (built-in self-test), at-speed scan testing and parameter testing. Experimental results demonstrate that the proposed technique can gain high fault coverage and test compression ratio, which are 97.39% and 30%, satisfying the project demands.

I. Introduction
II. Background
III. Dft Features
IV. Experimental Results
V. Conclusion
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