58 Miniaturization and Optimization of Power Consumption in CNTFET Circuits for Use in the Manufacture of Artificial Neural Brain Cortex

This article is on the CNTFET structure and to optimize power consumption and miniaturization of CNT based transistors as possible. The parameters of such structure and their impact on the on and off-current mode has been study to use in future construction of Low Operating Power circuits (LOP) , especially excitatory neurons in the brain cortex nerve (synthetic cortex). Our simulations implement in HSPICE environment and on the n - i - n CNTEFT. We have spice models to use CNTFET simulation [6].