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International Conference on Computer and Automation Engineering, 4th (ICCAE 2012)

Jianhong Zhou
Jianhong Zhou
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This paper describes about the design methodology for reducing router power consumption with the aid of RTL clock gating technique. It causes inactive clocked elements to have clock gating logic (automatically by using cadence tool) which reduces power consumption on those elements to zero when the values stored by those elements are not changing. This technique allows a variety of features such as easily configurable, automatically implemented clock gating which allows maximal reduction in power requirements with minimal designer involvement and software involvement. In this paper, source code was written in Verilog (Hardware Descriptive language) and it was synthesized in Xilinx 9.1i version, simulated in Modelsim 6.6 version and clock gating was applied by using Cadence.

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