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ASME Press Select Proceedings

International Conference on Advanced Computer Theory and Engineering, 4th (ICACTE 2011)

By
Yi Xie
Yi Xie
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ISBN:
9780791859933
No. of Pages:
840
Publisher:
ASME Press
Publication date:
2011

The rasterizer unit is the most time-consuming architecture in 3D graphic pipeline due to its complicated computations so objects polygonal meshes rasterization is a significant bottleneck in software-based rendering. This unit is responsible for computing pixel values based on illumination, surface material, texture and ordering of the objects in scene. In this paper, we present an effective architecture for a hardware accelerator for rasterizing with Gouraud shading and perspective-corrected bilinear texture mapping features. We have synthesized and implemented the rasterizer on a FPGA PCI board for benchmarking purpose.

Abstract
Keywords
1. Introduction
2. Key Elements of 3D Rasterizer
3. Structure of Our Rasterizer
4. Performance and Results
5. Conclusion of Feature Works
6. References
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