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ASME Press Select Proceedings

International Conference on Mechanical Engineering and Technology (ICMET-London 2011)

Editor
Garry Lee
Garry Lee
Information Engineering Research Institute
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ISBN:
9780791859896
No. of Pages:
906
Publisher:
ASME Press
Publication date:
2011

Recent microprocessors consume significant energy to provide high performance. For this reason, the energy-aware techniques should be applied to high performance embedded processors. Especially, the energy consumed in caches accounts for a significant portion of total processor energy. Therefore, many researchers have focused on the energy optimization techniques for caches. The filter cache scheme is one of the most famous schemes to reduce the energy consumption in the cache. However, the filter cache scheme causes performance degradation inevitably. In this paper, we propose the technique to improve the hit rates of level-0 data cache based on the filter cache scheme....

Abstract
Keywords
Introduction
Proposed Architecture
Experiments
Conclusion
Acknowledgment
References
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