International Conference on Mechanical Engineering and Technology (ICMET-London 2011)
132 Improving the Hit Rates of Level-0 Data Cache for Energy-Efficient Embedded Processors
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Recent microprocessors consume significant energy to provide high performance. For this reason, the energy-aware techniques should be applied to high performance embedded processors. Especially, the energy consumed in caches accounts for a significant portion of total processor energy. Therefore, many researchers have focused on the energy optimization techniques for caches. The filter cache scheme is one of the most famous schemes to reduce the energy consumption in the cache. However, the filter cache scheme causes performance degradation inevitably. In this paper, we propose the technique to improve the hit rates of level-0 data cache based on the filter cache scheme. To reduce the performance degradation due to the filter cache scheme, the modified victim cache is appended in the proposed cache scheme. According to our experiments, the proposed scheme reduces the energy consumption in the data cache compared to the traditional cache scheme by 10% on the average. Moreover, it improves the performance by 3% compared to the conventional data filter cache scheme, on average.