33 A New Architecture with High Logic Utilization and Simple Precedence Constraints for Dynamically Reconfigurable FPGAs Available to Purchase

Dynamically reconfigurable FPGAs (DRFPGAs) dramatically improve logic utilization by using time-sharing logic. In order to use DRFPGAs the precedence constraints must be followed. It is a problem with high complexity to partition a circuit for implementation on a DRFPGA. In this paper, we present a new DRFPGA architecture with simpler precedence constraints than the conventional Xilinx DRFPGA. This is achieved by controlling the clock of the flip-flop and micro register. We also modify the hardware of Xilinx FPGA to improve its logic utilization and execution efficiency.