18 BIST for SOC Interconnects Using Extended Serial TAM in IEEE 1500 Standard Available to Purchase

With advance in technology and working frequency reaches gigahertz, designing and testing interconnects becomes an important issue. In this paper, we proposed BIST based architecture to at-speed test of crosstalk faults for SOC interconnects. This architecture includes IEEE 1500 wrapper in which enhanced cells intended for Multiple Victim Test (MVT) model test patterns generation and analysis test responses. MVT models a set of faults caused by crosstalk effects. One new instruction is used to control cells and TPG controller in wrapper serial TAM in order to fully comply with conventional IEEE 1500 standard.