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ASME Press Select Proceedings
International Conference on Computer and Electrical Engineering 4th (ICCEE 2011)
By
Jianhong Zhou
Jianhong Zhou
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ISBN:
9780791859841
No. of Pages:
698
Publisher:
ASME Press
Publication date:
2011

With advance in technology and working frequency reaches gigahertz, designing and testing interconnects becomes an important issue. In this paper, we proposed BIST based architecture to at-speed test of crosstalk faults for SOC interconnects. This architecture includes IEEE 1500 wrapper in which enhanced cells intended for Multiple Victim Test (MVT) model test patterns generation and analysis test responses. MVT models a set of faults caused by crosstalk effects. One new instruction is used to control cells and TPG controller in wrapper serial TAM in order to fully comply with conventional IEEE 1500 standard.

Abstract
Key Words
1. Introduction
2. Test Patterns for Crosstalk Faults
3. Boundary Cells with Capable of At-Speed Test
4. Proposed Test Architecture
5. Simulation Results
6. Summaries
References
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