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ASTM Selected Technical Papers
Semiconductor Fabrication: Technology and Metrology
By
DC Gupta
DC Gupta
1
Editor
.
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ISBN-10:
0-8031-1273-4
ISBN:
978-0-8031-1273-5
No. of Pages:
485
Publisher:
ASTM International
Publication date:
1989

The use of arsenic ion implant for a low sheet resistance and deep junction buried layer process was investigated. Appropriate ion doses and energy were found to obtain the desired buried layer profile using a pre-implant oxide. A low temperature (1050°C) oxidation was employed to remove the highly damaged surface region after diffusion/anneal of the arsenic implant. Damage was characterized after the buried layer process and epitaxial growth. The electrical performances and relative yield of the bipolar devices made from implanted and deposited (solid-source) arsenic buried layer were compared. The results indicated that implanted buried layer produced almost defect free epitaxial layer in the subsequent processing.

1.
Dreeban
A.
and
Schajko
A.
On a Relationship Between Substrate Perfection and Stacking Faults in Homo Epitaxial Silicon
”,
RCA Review
 0033-6831, Vol.
44
, p. 217,
1983
2.
Prussin
S.
,
Margolese
D. I.
, and
Tauber
R. N.
The Nature of Defect Layer Formation for Arsenic Ion Implantation
”,
J. Appl. Phys.
 0021-8979, Vol.
54
, No.
5
, p. 2316,
1983
3.
Hirao
T.
,
Fuse
G.
,
Inoue
K.
,
Takayanagi
S.
,
Yaegashi
Y.
, and
Ichikawa
S.
The Effect of the Recoil-Implanted Oxygen in Si on The Electrical Activation of As After Through-Oxide Implantation
”,
J. Appl. Phys.
 0021-8979, Vol.
50
, No.
8
, p. 5251,
1979
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