Chemical Mechanical Polishing (CMP) of copper in trenches and vias of patterned silicon wafers is routinely used in CMOS processes as well as MEMS applications. Although the main goals of CMP are to achieve a planar surface at the nano-scale without scratches, it is generally the case that copper is preferentially polished, a condition called dishing and erosion, relative to the pattern geometry. We have measured dishing and erosion of electroplated copper on patterned silicon wafers with specially-designed patterns containing combinations of line-width and density. One hundred millimeter diameter wafers were patterned using a standard etching process and electroplated with copper. The polishing was done on a modified laboratory-scale bench top polisher which allows ranges of normal loads and velocities. A commercial pad (Rodel IC1000 plain) and slurry were used along with a slurry-delivery rate fixed by a peristaltic pump. The pad conditioning and other process parameters were chosen to represent those used in standard industrial practice. Dishing and erosion were measured as a function of the pattern geometry and polishing conditions. The measured dishing and erosion were then compared to other models.

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