Next generation integrated circuits (IC’s) will require the use of porous dielectric materials with shear strengths much lower than the currently used dense silicon dioxide. The high friction of CMP (chemical mechanical polishing) may damage these porous dielectric materials. This research is being performed to define the nanoscale source of this poorly understood CMP friction to enable development of less damaging CMP processes. It is proposed that the nanoscale friction on the IC from CMP is a variable combination of two-body pad nanoasperity to IC contact and three-body nanocontact of the slurry particle between the pad nanoasperity and the IC surface. This research uses a combination of individual nanoscale friction measurements for CMP of SiO2, an analytical model to sum these effects, and bench scale CMP experiments to guide the research and validate the model.

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