Planarization needs for integrated circuit (IC) technology focus on feature-scale (100nm–1μm) and die-scale (5mm-20mm) dimensions. As three-dimensional (3D) integration moves from die-by-die assembly to wafer-level integration to provide a higher density of low electrical parasitic vertical interconnects (or vias), wafer-level planarization needs to be considered. Planarization needs depend upon the 3D technology platform approach (such as (1) blanket bonding followed by inter-wafer interconnect processing or via-first processing followed by bonding and thinning to expose the vias and (2) the number of wafers in a 3D stack) and the processing conditions used in fabricating the wafers to be 3D integrated (in particular, the built-in stress levels and post-bonding thermal processing budget). This invited presentation includes a summary of the current interest in wafer-level 3D integration in both the academic and industrial research community. Wafer-level planarization issues with different technology platforms are presented, and the limited results presented in the literature to date are summarized. The importance of wafer-level planarization compared to bonding, thinning and wafer-to-wafer alignment is discussed.
Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs
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Gutmann, RJ, McMahon, JJ, & Lu, J. "Global Planarization Requirements for Wafer-Level Three-Dimensional (3D) ICs." Proceedings of the World Tribology Congress III. World Tribology Congress III, Volume 2. Washington, D.C., USA. September 12–16, 2005. pp. 365-366. ASME. https://doi.org/10.1115/WTC2005-63492
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