Recent investigations on the fabrication of ultra-thin silicon (Si) wafers using wire-electrical discharge machining (wire-EDM) were observed to possess some inherent limitations. This includes severe thermal damage, kerf-loss, and low slicing rate, which could be detrimental towards realizing actual practical applications. The extent of thermal damage, kerf-loss, and slicing rate largely depends on the process parameters such as open voltage (OV), servo voltage (SV), and pulse on-time (Ton). Therefore, choosing the optimal parameters that pertain to minimum thermal damage and kerf-loss while maintaining a higher slicing rate is the key to further excel in the fabrication of Si wafers using wire-EDM. Therefore, the present study is an effort to analyze and identify the optimal parameters that relate to the most effective Si slicing in wire-EDM. A central composite design (CCD) based response surface methodology (RSM) was used for optimizing the process parameters. The capability to slice Si wafers in wire-EDM was observed to be highly influenced by the discharge energy, which had a positive impact on the overall responses. The severity of thermal damages was observed to be mainly dominated by the variation in open voltage and Ton due to the high diffusion of thermal energy into the workpiece, which led to intense melting and subsequent re-solidification. The parametric optimization resulted in OV = 84.32 V, SV = 42.98 V and Ton = 0.62 μs as the most feasible parameter that relates to comparatively high slicing rate (0.65 mm/min), low kerf-loss (280 μm) and thermal damage (18 μm) for a given machine. In general, with a decrease in spark energy slicing rate and thermal damage decreases whereas, kerf-loss increases. When spark energy decreases by 83%, there is a nearly 55% decrease in slicing rate and thermal damage and a 10% increase in kerf-loss.

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