Silicon is an excellent transparent material for building IR micro-optical elements such as holographic and blazed gratings, and curvilinear micro-lenses. Shaping this material in 3D with mirror quality finish and single-digit microscale resolution is challenging due to its brittleness and high-melting point. To achieve these patterning characteristics, electron-beam grayscale lithography is typically selected to pattern a 2.5D feature onto a resist thin-film. Subsequently, the film features are transferred into the underlying silicon substrate by deep-reactive ion etching (DRIE) . Small variations in the resist thickness lead to large shape distortions and reduced patterning repeatability. Further, the direct-write nature of e-beam lithography provides for slow throughput. Developing an alternative, parallel and scalable method to nanopatterning silicon with 2.5D geometrical control may impact emerging areas such as the design of sub-wavelength photonic and micro-optic elements for silicon photonics applications.
Micro and nanoscale patterning of inorganic semiconductors (e.g. Silicon) requires traditional micromachining processes such as plasma-assisted etching (e.g. DRIE) and wet-etching (e.g. KOH etching). Neither of the aforementioned processes offer the capability to control the geometry in 3D with resolution in the nanoscale range. Thus, it is desirable to develop a low-temperature, low-stress and ambient approach to nanostructuring silicon in 3D. Wet etching approaches are good candidates for achieving such goal because they bypass the need for high-temperature processing and stressing materials beyond the elastic limit. Yet, they still rely on lithographical steps and offer limited sidewall control, restricting the scope of features it can produce.
In recent literature, catalyst-based wet etching processes such as metal-assisted chemical etching (MACE) have been shown to pattern high-aspect ratio structures in semiconductors [2–3]. Some researchers have achieved control over the etch profile and etching direction, generating a limited set of interesting 3D objects [4–6]. The degrees of freedom in MACE patterning are still highly constrained due to limited control of the catalyst motion. Additionally, thin-film based MACE relies on intermediate 2D masking steps to pattern the catalyst which are often lithographical. Thus, this indirect approach to patterning silicon increases lead time and processing costs.
In this paper, Mac-imprint, a direct imprint configuration of MACE, is introduced to overcome these fundamental barriers. It relies on the use of a catalytic stamp immersed in the etchant and brought against a silicon chip to selectively dissolve it at contact points. Stamps can be reused multiple times to pattern substrates with lifetimes that are dependent solely on its chemical and mechanical degradation. This process is inherently non-lithographic and occurs at room temperature. As a demonstration of its high-resolution capabilities, silicon wafers were patterned with a sinusoidal wave whose pitch and amplitude were 1 μm and 250 nm, respectively. The patterned surface RMS error from the ideal surface was measured to be 13 nm. The key drawback of this approach is the generation of porous defects near the vicinity of the contact interface between stamp and substrate. Its spatial distribution is qualitatively discussed in the context of the diffusion model of MACE .