Electrothermal transport and crystallization dynamics govern the speed and reliability of multibit phase change memory (PCM). This work develops a transient simulation code incorporating the nanoscale electrical, thermal, and crystalline growth models to investigate various cell structures and programming strategies. The simulation evaluates the multibit performances of two standard PCM structures, the “mushroom” cell and the “confined pillar” cell, with feature sizes smaller than 40nm. This paper implements the simulation code to explore a more compact and reliable architecture, the stacked vertical cell, for precise control of the Joule heating and the intermediate resistance states. For an electrode area of 10nm × 20nm, very low programming current of 60μA – 90μA generates sufficient heating power to amorphize the phase change elements sequentially, resulting four distinct resistance levels for multibit applications.

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