The increase in the integration of interconnect wiring, as well as the high level of current densities are resulting in increased concerns about hot spot formation due to Joule heating in the metal lines of microprocessors. This temperature rise poses a major challenge in maintaining the quality and reliability of future devices, requiring a focus on physics based approaches for rapid and accurate thermal analysis of interconnect architectures. This work investigates the problem of transient Joule heating in a three-dimensional array of copper interconnects embedded in dielectric layers of SiO2 and Si3N4 using Proper Orthogonal Decomposition (POD) as the reduced order modeling approach. The case of natural convection was assumed on the boundaries. For validation, the results were compared with a three-dimensional finite volume model developed in Fluent and good agreements models were observed. While the Fluent model required hours of computational time, the POD based model predictions were achieved within seconds.

This content is only available via PDF.
You do not currently have access to this content.