Substituting the active inductor for the passive inductor to integrate the 5.8GHz bandpass filter into a system-on-chip (SoC) circuit is a feasible solution to reduce the filter chip area, increasing the application competition. The bandpass filter circuit in simulation with TSMC 0.18um CMOS process models and Agilent simulation software exhibits the good performance such as an input return loss (S11) of −34.26dB, an output return loss (S22) of −17.49dB, a bandpass gain (S21) of −4.33dB, a noise figure (NF) of 18.91dBm, a 1-dB compression point (P1dB) of −23dBm, a third-order intercept point (IIP3) of −15.83dBm, and the power dissipation in 19.44mW under 1.8V power-supply operation. In addition, the 3-dB bandpass bandwidth is 300MHz. The final dimension of this chip is approximate to 680×530μm2.

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