Quantifying the contribution of the hot carrier effect (HCE) and the negative bias temperature instability (NBTI) effect in PMOSFET device reliability is an urgent target, especially as the dual poly-gate implantation and the novel oxide growth recipe is derived. At this stage, the PMOS gate-oxide thickness is thinner than before, therefore, the implanted boron or BF2 is possible to penetrate from poly gate to surface channel. Furthermore, the implant source contains the plenty ionized hydrogen. This material is easily to be trapped in the gate oxide or bonded with the surface-channel silicon. The amount of interface state concentration, Nit, or oxide trap concentration, Not, is increased. As a result, the threshold voltage of the PMOSFET will be shifted away from the design target. Therefore, the source/drain current will be influenced and this PMOSFET will usually exhibit an unstable state. In the worst case, the IC chip will fail or stop working. This negative bias temperature instability (NBTI) effect has the tremendous impact to the PMOSFET performance.

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