In this work, the mechanical behavior of a typical UV curable solder mask material has been explored as a function of ultra violet (UV) curing time, testing temperature, and isothermal aging exposure. Mechanical testing has been performed using standard tensile testing. For the tensile testing, a specimen preparation procedure has been developed to make 80 × 3 mm uniaxial tension test samples with a defined thickness (e.g. 0.30 mm), and both stress-strain and creep tests were performed. The solder mask test specimens were prepared in a unique way and no release agent is required to extract them from the mold. The mechanical behavior changes of the solder mask material were recorded for different curing profiles including various durations of UV exposure and subsequent isothermal curing. The results showed that an optimum UV exposure time was critical to provide acceptable mechanical properties. In addition, the stress-strain and creep behavior of the solder mask were recorded for various temperatures from 25 to 125 °C, and the mechanical properties were found to degrade significantly at elevated temperatures as expected. The experimental results showed that variations of thermal curing profile (curing temperature and time) also change the mechanical properties significantly, so that solder masks have a very small optimum processing window. Finally, the effects of isothermal aging at 100 °C on the material behavior were characterized for different aging times. Using the recorded data, the changes in the elastic modulus, strength, and creep rate were characterized as a function of aging time. Significant variations were observed in the elastic modulus (250%) and ultimate strength (150%) of the aged samples.

For design of automotive airbag electronic control units (AB ECU), it is essential to have a validated and reliable finite element (FE) simulation model in place in order to allow already in an early design stage for the accurate prediction of the ECU’s structural vibration behavior. A “bottom-up” approach which described in the ASME guide for verification and validation (ASME V&V 10-2006) is applied for the validation of the AB ECU simulation model. The AB ECU is decomposed into different assembly level. Single printed circuit board (PCB) is the lowest elementary component level. In the PCB level simulation and validation, the influence of in-plane pre-stress on PCB’s transverse vibration characteristic has been encountered, but it has been found out that the source of the in-plane pre-stress can not be explained by classical beam/plate theory. Analysis and simulation for PCB fixation reveals that the fundamental source of the in-plane pre-stress is structure’s geometric nonlinearity.

As semiconductor device feature size scales and circuit performance increases, power dissipation and thermal management are becoming very important. Attention to thermal considerations is required throughout the chip development cycle from preliminary architecture planning to deployment on customer board and beyond. This paper describes a versatile thermal test vehicle that can be used to address these requirements. We discuss the architecture and implementation of a specially designed test-vehicle chip, followed by its operation. The programmability and flexibility of this vehicle will be highlighted. In addition, we cover other usage of this vehicle which includes modelling of chip-level thermal behavior with different floorplan, simulating thermal loads in IoT FPGA applications, cross-calibrating thermal numerical simulators with measured silicon data and evaluating the thermal impact of different package form-factor / material (such as thermal interface material) and cooling solutions. The abovementioned chip was fabricated using 0.18um technology and assembled in a flip-chip package. The reminder of this evaluation system is a simple, inexpensive tester from which a software is run to program the chip and to measure the spatial & temporal temperature values. Measured thermal data from different use cases are presented in this paper.

Thermal Interface materials are crucial elements for packaging of power electronics. In particular, development of high temperature lead free die-attach thermal interface materials for silicon carbide wide bandgap power electronics is a challenge. Failures of power electronics package modules often occur at die-attach areas. Among major options, sintered silver shows advantages in ease of applications. Cost, reliability, and integration are concerns for technology implementation. The current study first discusses issues and status reported in literatures. Then it focuses on cost reduction and improvement of sintered silver using enhancement structures at micro and nano scales. A few design architectures are analyzed by finite element methods. The feasibility of strengthening edges and corners is also assessed. The downside of potential increase of unfavorable stresses to accelerate void coalescence would be discussed in conjunction with design concept of power electronics package modules for paths of solutions in the form of integrated module systems.

The rapid growth in cloud computing, the Internet of Things (IoT), and data processing via Machine Learning (ML), have greatly increased our need for computing resources. Given this rapid growth, it is expected that data centers will consume more and more of our global energy supply. Improving their energy efficiency is therefore crucial. One of the biggest sources of energy consumption is the energy required to cool the data centers, and ensure that the servers stay within their intended operating temperature range. Indeed, about 40% of a data center’s total power consumption is for air conditioning[1]. Here, we study how the server air inlet and outlet, as well as the CPU, temperatures depend upon server loads typical of real Internet Protocol (IP) traces. The trace data used here are from Google clusters and include the times, job and task ID, as well as the number and usage of CPU cores. The resulting IT loads are distributed using standard load-balancing methods such as Round Robin (RR) and the CPU utilization method. Experiments are conducted in the Data Center Laboratory (DCL) at the Georgia Institute of Technology to monitor the server outlet air temperature, as well as real-time CPU temperatures for servers at different heights within the rack. Server temperatures were measured by on-line temperature monitoring with Xbee, Raspberry PI, Arduino, and hot-wire anemometers. Given that the temperature response varies with server position, in part due to spatial variations in the cooling airflow over the rack inlet and the server fan speeds, a new load-balancing approach that accounts for spatially varying temperature response within a rack is tested and validated in this paper.

Creep response of joints bonded with single-layered pressure sensitive adhesives (PSAs) was investigated in this study. PSAs are becoming more and more popular in the electronic industry as bonding media because of their ease of design, fast accurate bonding, environmentally-friendly bonding and ease of reworking. Such adhesive bonds are expected to experience complex, sustained loading conditions in service; e.g. loading due to large mass components, shock, temperature, or alignment mismatch of substrates. Stress-strain behavior of PSA bonding assembly has been extensively studied through experiments and simulations, including the effects of loading conditions (loading rate and temperature), PSA configurations (thickness of adhesive and single/double-layered PSAs), and bonding substrate surface properties (substrate material and surface roughness). However, the literature regarding the creep response of PSA-bonded assemblies is lacking and there is no literature on modeling methodologies for the creep response of such bonding systems. Similar to the stress-strain behavior of PSA-bonded assemblies, the creep response includes transitions between multiple hardening and softening phases. Experimental results indicate that the secondary creep rate can change by up to two orders of magnitude after each transition, which is too significant to ignore when estimating the creep deformation of joints bonded with this material system. The number of transitions is related to the configuration of the PSA system, i.e. the single-layered PSA has one transition while double-layers PSAs may have multiple transitions due to the additional interface(s) introduced by the carrier layer. This unique secondary creep behavior comes from the competition between hydrostatic stress relaxation and strain hardening, caused by cavitation and fibrillation processes, respectively. The total stress applied on the joint is equal to the summation of deviatoric stress and hydrostatic stress. An advanced model based on the stress-strain ‘block’ model [5–7] is developed for evaluating the creep response. This model has the capability to control the initiation and growth of cavities in the bulk of the PSA and at the interface between PSA and substrate. This model is able to capture the nonlinear visco-plastic behavior of the PSA fibrils and estimate the effects of flexible carrier layer on the transitions in creep curves. The model prediction shows reasonable agreement with experimental results in terms of the characteristic features in creep strain histories.

In this study, we have conducted a combined numerical and experimental study on the Poisson’s ratio of SAC lead free solders. The Poisson’s ratio (PR) is one of the basic mechanical properties used in many material constitutive models. Although often not measured, it is important property in many finite element method (FEM) calculations. The value of the Poisson’s ratio of SAC lead free solders is relatively unexplored compared to other material properties, and for FEA simulations it is typically assumed to be v = 0.3. In the current work, we have shown the effects of the chosen value of the solder joint Poisson’s ratio on the finite element results for BGA components subjected to thermal cycling. In the finite element models, the reliability predictions were based on the Morrow-Darveaux energy-based fatigue model. Several sizes (5, 10, 15 mm) of PBGA components with SAC305 solder joints with 0.4 and 0.8 mm spacing were modeled. The packages were subjected to a time dependent cyclic temperature distribution from −40 to 125 °C. The package assemblies were assumed to be in a stress-free state at 25 °C (room temperature), with no residual stresses induced in the manufacturing process. The simulation results have demonstrated that for specified range of Poisson’s ratio values of 0.15 < v < 0.40, the solder Plastic Work varied over 20% and the Predicted Reliability Varied over 50%. To determine the actual Poisson’s ratio experimentally, uniaxial tensile stress-strain tests were carried out on SAC305 (96.5Sn3.0Ag0.5Cu) specimens using a micro tension/torsion testing machine with two strain rates (0.0001, and 0.00001 (sec −1 )), four testing temperatures (T = 25, 50, 75, 100 °C), and several durations of prior aging at T = 125 °C. Deformations and strains in axial and transverse directions were measured using strain gages with automatic data acquisition from LabVIEW software. The recorded transverse strain vs. axial strain data were then fit with a linear regression analysis to determine the Poisson’s ratio values. A test matrix of experiments was developed to study the effects of temperature, strain rate, alloy composition, and solidification cooling profile on the value of solder Poisson’s ratio. The Poisson’s ratio was found to increase with increasing temperature, and decrease with increasing strain rate. Using a slower solidification cooling profile led to an increase in the solder Poisson’s ratio value. Finally, the microstructural coarsening that occurs during isothermal aging lead to an increase in the Poisson’s ratio.

Flip chip (FC) packaging techniques in modern power electronics have enabled increased power density in module performance, but mechanical stresses induced by thermal expansion during inherent operating conditions in the power devices and packages create a need for understanding thermomechanical fatigue mechanisms that lead to reliability concerns. Moreover, in actual use, these mechanical stresses impact the reliable lifetime alongside thermal factors (such as diffusion and microstructural transformation) and other process history effects. This amalgam of damage inducing phenomena make development of a concise association between damage, fatigue, and stress factors difficult to determine. For reliability demonstration under fatigue loading, accelerated life testing (ALT), such as Thermal Cycling (TC), are commonly used in industry; however, long duration and expensive equipment required for TC limit its utility, especially when considering the high cost of wide-bandgap devices and modules, and the limitation of high temperature (> 150°C) testing standards. As a result, alternative test methodologies are needed to provide faster, cheaper, and design integrable reliability determination. In this work, an accelerated test methodology is introduced and designed to simulate these mechanical stresses at isothermal conditions, which is demonstrated using test chips that are analogous to power devices. By stressing these devices in a controlled environment, mechanical stresses become de-coupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device-relevant, flip-chip solder interconnects while monitoring cycles-to-failure (CTF). Also, Finite Element Analysis (FEA) is used to extract various damage metrics of different solder materials (including PbSn37/63, SAC305 and Nano-silver) in both thermal operation and the introduced alternative mechanical testing conditions. In doing so, test protocol translations to common qualification tests (or use condition thermal profiles) can be determined and are validated using the mechanical shear stress testing method. Plastic work density and maximum shear were calculated in the critical solder interconnects for different isothermal mechanical testing temperatures (22°C, 75°C, 100°C and 125°C) and the results are compared with the simulation results of different TC test conditions. This reliability determination with failure parameter isolation allows for improved integration with FEA modeling for a priori reliability prediction during the design process.

Stress sensors have shown potential to provide “health monitoring” of a wide range of issues related to packaging of integrated circuits, and silicon carbide offers the advantage of much higher temperature sensor operation with application in packaged high-voltage, high-power SiC devices as well as both automotive and aerospace systems, geothermal plants, and deep well drilling, to name a few. This paper discusses the theory and uniaxial calibration of resistive stress sensors on 4H silicon carbide (4H-SiC) and provides new theoretical descriptions for four-element resistor rosettes and van der Pauw (VDP) stress sensors. The results delineate the similarities and differences relative to those on (100) silicon: resistors on the silicon face of 4H-SiC respond to only four of the six components of the stress state; a four-element rosette design exists for measuring the in-plane stress components; two stress quantities can be measured in a temperature compensated manner. In contrast to silicon, only one combined coefficient is required for temperature compensated stress measurements. Calibration results from a single VDP device can be used to calculate the basic lateral and transverse piezoresistance coefficients for 4H-SiC material. Experimental results are presented for lateral and transverse piezoresistive coefficients for van der Pauw structures and p- and n-type resistors. The VDP devices exhibit the expected 3.16 times higher stress sensitivity than standard resistor rosettes.

The objective of this work is to introduce the application of an artificial neural network (ANN) to assist in the evaporative cooling in data centers. To achieve this task, we employ the neural network algorithms to predict weather conditions outside the data center for direct evaporative cooling (DEC) operations. The predictive analysis helps optimize the cooling control strategy for maximizing the usage of evaporative cooling thereby improving the efficiency of the overall data center cooling system. A typical artificial neural network architecture is dynamic in nature and can perform adaptive learning in minimal computation time. A neural network model of a data center was created using operational historical data collected from a data center cooling control system. The neural network model allows the control of the modular data center (MDC) cooling at optimum configuration in two ways. First way is that the network model minimizes time delay for switching the cooling from one mode to the other. Second way, it improves the reaction behavior of the cooling equipment if an unexpected ambient condition change should come. The data center in consideration is a test bed modular data center that comprises of information Technology (IT) racks, Direct Evaporative cooling (DEC) and Indirect Evaporative Cooling (IEC) modules; the DEC/IEC are used together or in alternative mode to cool the data center room. The facility essentially utilizes outside ambient temperature and humidity conditions that are further conditioned by the DEC and IEC to cool the electronics, a concept know as air-side economization. Various parameters are related to the cooling system operation such as outside air temperature, IT heat load, cold aisle temperature, cold aisle humidity etc. are considered. Some of these parameters are fed into the artificial neural network as inputs and some are set as targets to train the neural network system. After the training the process is completed, certain bucket of data is tested and further used to validate the outputs for various other weather conditions. To make sure the analysis represents real world scenario, the operational data used are from real time data logged on the MDC cooling control unit. Overall, the neural network model is trained and is used to successfully predict the weather conditions and cooling control parameters. The prediction models have been demonstrated for the outputs that are static in nature (Levenberg Marquardt method) as well as the outputs that are dynamic in nature i.e., step-ahead & multistep ahead techniques.

Active power cycling is a standardized and well-established method for reliability assessment and product qualification in power electronics technologies. Repetitive pulses of load current are applied to cause cyclic thermal swings in the p-n junction and in the whole semiconductor device. They induce thermo-mechanical stresses, which ultimately leads to the typical interconnect failure in the ‘devices under test’. However, these tests are insensitive with respect to new automotive system architectures, in which power electronics devices are exposed to additional loads besides the intrinsic thermal swings. The trends in power electronics towards miniaturization, higher power density, heterogeneous system integration, and the deployment of power electronics in harsher environments combined with longer lifetime and higher uptime requirements strongly increase the reliability demands in general and the need for more improved reliability assessment methodologies in particular. The new testing methods shall be more comprehensive and more efficient, i.e., they shall simultaneously cover the real service conditions better and reduce testing time. One promising approach is the combination of loading factors — such as the superposition of active power cycling by passive thermal cycles. Both loading factors are well-known to cause most relevant failure mechanisms in power electronics. In reality, the power electronic devices are exposed to both factors simultaneously. Hence, this load case should also be replicated in the test. The paper will report a systematic investigation of such superimposed test schemes, which cover the case of self-heating and passive heating (from neighboring elements) of the power electronics devices under real service conditions. Typical discrete power electronics components in TO-200 packages are selected as test vehicles as they are likewise relevant for the domains of consumer or automotive electronics. The paper details the test concept and discuss the quantitative and qualitative test results.

The increasing thermal demands in power electronic systems require the application of high temperature die attach materials. Transient Liquid Phase Sintered (TLPS) paste-based solder alloys have been demonstrated to effectively manage the thermal and mechanical load requirements of power modules. The microstructural features of these alloys provide interconnects with the necessary strength required to sustain high loads at high temperatures. To properly understand the influence of microstructure on mechanical behavior of these alloys, single lap shear experiments were performed on a TLPS system consisting of Copper and Tin particles (Cu-Sn). Nano-indentation measurements were performed on intermetallic phases of the TLPS, and the results obtained from lap shear testing and nano-indentation measurements are presented.

With the larger size of Ball Grid Array (BGA) solder joints, the available volume for underfilling is significantly increased. Although the size of the solder joints and package dimension governs the volume of underfill material, the larger 2 nd level solder interconnects are more susceptible to thermal fatigue with certain underfills and thermal profiles. In this study, BGA packages were underfilled with two dedicated underfill materials and two soft materials used as conformal coatings and encapsulants in electronic products. Each of the selected materials was subjected to two thermal profiles, one with low mean temperature and a second with a high mean temperature. The variation in mean cyclic temperature demonstrates the influence of temperature dependent behavior of each underfill material on the loads solder joints experience in a BGA package. Material characterization was performed on the package and underfill materials and incorporated into finite element models. The influence of underfill material glass transition temperature (T g ) was found to be a critical factor on fatigue endurance of solder interconnects. Fatigue crack orientation within solder joints were found to be aligned with axial (normal) direction for BGAs with high CTE underfill materials. Simulations determined the magnitude of axial loading associated with each underfill material properties responsible for reducing fatigue life. The results developed in this paper reveal the factors associated with reduced fatigue endurance of certain underfill materials under temperature profiles with mean temperature conditions and contribute to the development of new criteria of underfill material selection for 2 nd level interconnects.

Nowadays microelectronic packaging has become a billion dollar business. Due to the increased material and production costs per package, manufacturing yield loss in this state-of-art business is expected to be at a bare minimum which is tough to persevere in a high volume manufacturing environment. Additionally, high performance and varied power computing needs in the electronic business demands microprocessors with different form factors and complex package designs. One of the most common joint which is extensively used in such a complicated package is the polymer to metal bonding. In the latest technology products involving high package warpage, interfacial bonding has to be strong enough to withstand the dynamic warpage and high mechanical stresses associated with it and hence the reliability of polymer to metal adhesion is critical. In this paper, fundamental mechanisms related to adhesion phenomena of polymer-metal interface are proposed. Adhesive failure modes related to polymer-metal bonding and key variables influencing the bonding of silicone based polymer material to nickel electroplated on copper in an integrated circuit heat spreader assembly are experimentally studied. Factors modulating polymer to metal bonding including interfacial chemistry, surface contamination and material roughness are evaluated.

A low order fast running parametric analysis tool, ParaPower, was used to arrive at the design for a novel high voltage module. The low order model used a 3D nodal network to calculate device temperatures and thermal stresses. The model assumed heat flux generated near the top surface of each device which is then conducted through the packaging structure and removed by convection. The temperature distribution is used to calculate thermal stresses throughout the package. This co-design modeling tool, developed for rectilinear geometries, allowed a rapid evaluation of the package temperatures and CTE induced stresses throughout the design space. However, once the final design configuration was determined a detailed finite element analysis was performed to validate the design. This paper compares the results obtained using ParaPower to the FEA, demonstrating the usefulness of the parametric analysis tool. Results for both temperature and CTE induced stress are compared. Two different stress models are evaluated. One based on the more traditional planar module design, which assumes a substantial substrate or heat spreader on which the module is assembled. The other model is less restrictive, eliminating the requirement for a substrate. The FEA modeling was performed using SolidWorks beginning with a thermal analysis followed by a stress analysis based on the temperature solution. Both the values and the trends of the temperatures and stresses were evaluated. The temperature results agreed to within 3.2°C. The trends and sign of the stresses were correctly predicted, but the magnitudes were not. One of the significant advantages of ParaPower is the speed of the computation. The run time for the parametric analysis was roughly two orders of magnitude faster than the FEA. This made it possible to build the model and complete the parametric analysis of roughly 500 runs in less than a day.

Active liquid cooling is one of the most efficient and promising strategy for extreme thermal issues. As is the power source of the active liquid cooling system, a reliable and powerful micropump is urgently needed. In this study, we numerically studied the fluid flow of a hydrodynamic levitated micropump, considering the fluid flow in the motor. We found that the load capacity of the journal bearing is not influenced by the pump fluid flow. However, the pressure distribution of the journal bearing results in the dissymmetric pressure distribution in the spiral groove bearing, leading to worse stability of the axial levitation performance. The axial suspension force is at least 1.0N with the liquid film thickness of 15μm and is sufficient for the rotor with weight of 30g to be stably levitated in the fluid. Owing to the pressure difference inside the pump, the balance point of the rotor should be lower than the theoretical design when the micropump is operating.

In power electronic, ceramic substrates are used owing to their high thermal conductivity and dielectric strength. These substrates cannot withstand high voltages in the range of 20kV because thickness limitations inherit from the direct bond copper manufacturing method. This manufacturing process uses high temperature in order to bond the material layers. This negatively affects the material’s reliability due to the differing materials thermal expansion coefficients and the resulting residual stress. All this results in hindering the ceramic substrate in obtaining a higher dielectric strength. In contrast, cold gas spray has the potential to provide higher reliability due to its bonding mechanism, which relies on plastic deformation of solid particles at very high strain rates during impact to create a mechanical bond, forming a thick deposit. However, cold gas spray on ceramics has not been widely studied due to their brittleness and their inability to form a metallic bond. This work is aimed at providing an effective processing parameter map of the cold gas spray process to achieve a thick copper deposit on aluminum nitride on the basis of the comparison of experimental results with a numerical model and finite element simulation formulated in Mathematica and ABAQUS, respectively.

Thermal management has become more important as high-performance electronics have concentrated heat loads with current cooling technologies. This motivates the implementation of new cooling solutions to dissipate high heat levels from high-performance electronics. Evaporative cooling is one of the most promising approaches for meeting these future thermal demands. Thin-film evaporation promotes heat dissipation through the phase change process with minimal conduction resistance. In this process, it is important to design surface properties and structures that can minimize meniscus thickness, increase liquid-vapor interface area, and enhance evaporation performances. In this study, we thereby investigate thin-film evaporation by employing nanotextured copper substrates for varying thermal conditions. Specifically, we visualize the liquid spreading on the nanotextured surfaces using a high-speed imaging technique to quantify evaporative heat transfer for various designs. The permeability is calculated using an enhanced wicking model to account for the evaporation effect. The mass balance measurements allow us to calculate evaporation rates. Then, we employ infrared thermography to examine two-dimensional temporal temperature profiles of the samples during the evaporative wicking with a given heat flux. The combination of time-lapse images, evaporation rate measurements, and temperature profiles will provide a comprehensive understanding of evaporation performances of textured surfaces.

The study of solder joint reliability is one of the priority issues in electronic packaging. Solder alloys experience a highly nonlinear material behavior when subject to thermal cycling. It is a time consuming and difficult task to study the behavior of solder joints using experimental approaches. Finite element analysis provides a more efficient way to better understand the behavior of solder joints when accurate material models are available. With the developments of FEA algorithms and computer resources, the analysis approaches used for electronic packaging assemblies have evolved from 2-dimensional to 3-dimensional analyses, with far fewer assumptions needed in the fully 3D case. In this paper, we compare different FEA approaches covering various 2D and 3D modeling techniques to understand their advantages and drawbacks, especially as related to simulation accuracy and efficiency. Several models for a typical BGA assembly were prepared and analyzed including traditional mesh continuity models (2D slice model, 3D slice model, and 3D quarter model), as well as advanced models that employ Multi-Point Constraints (MPCs) and submodeling (global/local models). The Anand viscoplastic model was used for the solder joint material behavior in all of the FEA approaches. For the 3D mesh continuity models, an optimal analysis approach has been proposed to achieve the best balance between the accuracy of the simulation result and numerical efficiency of the simulation. Mesh transitions were used to maintain mesh continuity between regions of different mesh densities. A best choice of load step size was also found to reduce overall simulation time. For the analysis using MPCs to to bond different meshes, two improved modeling strategies have been proposed including a suggested ratio of contacting elements and the use of multiple-MPC contact pairs to reduce overall mesh density of the FE model. An improved simulation simulation strategy using submodeling has also been developed to obtain the best compromise in the global and local models between the mesh quality and load step size. An improved geometric simplification of the solder joint for use with energy based fatigue criteria was developed. Finally, comparisons and suggestions were made for the best analysis approach when using FEA techniques to predict the behavior of solder joints in PBGA packages.

As global demand for data centers grows, so does the size and load placed on data centers, leading constraints on power and space available to the operator. Cooling power consumption is a major part of the data center energy usage. Liquid cooling technology has emerged as a viable solution in the process of optimization of the energy consumed per performance unit. In this data center rack level evaluation, 2OU (Open U) hybrid (liquid+air) cooled web servers are tested to observe the effects of warm water cooling on the server component temperatures, IT power and cooling power. The study discusses the importance of variable speed pumping in a centralized coolant configuration system. The cooling setup includes a mini rack capable of housing up to eleven hybrid cooled web servers and two heat exchangers that exhaust the heat dissipated from the servers to the environment (the test rig data center room). The centralized configuration has two redundant pumps placed in series with heat exchanger at the rack. Each server is equipped with two passive (i.e. no active pump) cold plates for cooling the CPUs while rests of the components are air cooled. Synthetic stress load has been generated on each server using stress-testing tools. Pumps in the servers are separately powered using an external power supply. The pump speed is proportional to the voltage across the armature [1]. The pump rpm has been recorded with input voltages ranging from 11V to 17V. The servers are tested for higher inlet temperatures ranging from 25°C to 45°C which falls within the ASHRAE liquid cooled envelope W4 [2]. Variable pumping has been achieved by using different input voltages at respective inlet temperatures.