Exposure of lead free solder joints to high temperature isothermal aging conditions leads to microstructure evolution, which mainly includes coarsening of the intermetallic (IMC) phases. In our previous work, it was found that the coarsening of IMCs led to degradation of the overall mechanical properties of the SAC solder composite consisting of β-Sn matrix and IMC particles. However, it is not known whether the isothermal aging changes properties of the individual β-Sn and IMC phases, which could also be affecting to the overall degradation of properties. In this study, the aging induced variations of the mechanical properties of the β-Sn phase, and of Sn-Cu IMC particles in SAC solder joints have been explored using nanoindentation. SAC solder joints extracted from SuperBGA (SBGA) packages were aged for different time intervals (0, 1, 5, 10 days) at T = 125 °C. Nanoindentation test samples were prepared by cross sectioning the solder joints, and then molding them in epoxy and polishing them to prepare the joint surfaces for nanoindentation. Multiple β-Sn grains were identified in joints using optical polarized microscopy and IMCs were also observed. Individual β-Sn grains and IMC particles were then indented at room temperature to measure their mechanical properties (elastic modulus and hardness) and time dependent creep deformations. Properties measured at different aging time were then compared to explore aging induced degradations of the individual phases. The properties of the individual phases did not show significant degradation. Thus, IMC coarsening is the primary reason for the degradation of bulk solder joint properties, and changes of the properties of the individual phases making up the lead free solder material are negligible.

In this study, we have conducted a combined numerical and experimental study on the Poisson’s ratio of SAC lead free solders. The Poisson’s ratio (PR) is one of the basic mechanical properties used in many material constitutive models. Although often not measured, it is important property in many finite element method (FEM) calculations. The value of the Poisson’s ratio of SAC lead free solders is relatively unexplored compared to other material properties, and for FEA simulations it is typically assumed to be v = 0.3. In the current work, we have shown the effects of the chosen value of the solder joint Poisson’s ratio on the finite element results for BGA components subjected to thermal cycling. In the finite element models, the reliability predictions were based on the Morrow-Darveaux energy-based fatigue model. Several sizes (5, 10, 15 mm) of PBGA components with SAC305 solder joints with 0.4 and 0.8 mm spacing were modeled. The packages were subjected to a time dependent cyclic temperature distribution from −40 to 125 °C. The package assemblies were assumed to be in a stress-free state at 25 °C (room temperature), with no residual stresses induced in the manufacturing process. The simulation results have demonstrated that for specified range of Poisson’s ratio values of 0.15 < v < 0.40, the solder Plastic Work varied over 20% and the Predicted Reliability Varied over 50%. To determine the actual Poisson’s ratio experimentally, uniaxial tensile stress-strain tests were carried out on SAC305 (96.5Sn3.0Ag0.5Cu) specimens using a micro tension/torsion testing machine with two strain rates (0.0001, and 0.00001 (sec −1 )), four testing temperatures (T = 25, 50, 75, 100 °C), and several durations of prior aging at T = 125 °C. Deformations and strains in axial and transverse directions were measured using strain gages with automatic data acquisition from LabVIEW software. The recorded transverse strain vs. axial strain data were then fit with a linear regression analysis to determine the Poisson’s ratio values. A test matrix of experiments was developed to study the effects of temperature, strain rate, alloy composition, and solidification cooling profile on the value of solder Poisson’s ratio. The Poisson’s ratio was found to increase with increasing temperature, and decrease with increasing strain rate. Using a slower solidification cooling profile led to an increase in the solder Poisson’s ratio value. Finally, the microstructural coarsening that occurs during isothermal aging lead to an increase in the Poisson’s ratio.

Flip chip (FC) packaging techniques in modern power electronics have enabled increased power density in module performance, but mechanical stresses induced by thermal expansion during inherent operating conditions in the power devices and packages create a need for understanding thermomechanical fatigue mechanisms that lead to reliability concerns. Moreover, in actual use, these mechanical stresses impact the reliable lifetime alongside thermal factors (such as diffusion and microstructural transformation) and other process history effects. This amalgam of damage inducing phenomena make development of a concise association between damage, fatigue, and stress factors difficult to determine. For reliability demonstration under fatigue loading, accelerated life testing (ALT), such as Thermal Cycling (TC), are commonly used in industry; however, long duration and expensive equipment required for TC limit its utility, especially when considering the high cost of wide-bandgap devices and modules, and the limitation of high temperature (> 150°C) testing standards. As a result, alternative test methodologies are needed to provide faster, cheaper, and design integrable reliability determination. In this work, an accelerated test methodology is introduced and designed to simulate these mechanical stresses at isothermal conditions, which is demonstrated using test chips that are analogous to power devices. By stressing these devices in a controlled environment, mechanical stresses become de-coupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device-relevant, flip-chip solder interconnects while monitoring cycles-to-failure (CTF). Also, Finite Element Analysis (FEA) is used to extract various damage metrics of different solder materials (including PbSn37/63, SAC305 and Nano-silver) in both thermal operation and the introduced alternative mechanical testing conditions. In doing so, test protocol translations to common qualification tests (or use condition thermal profiles) can be determined and are validated using the mechanical shear stress testing method. Plastic work density and maximum shear were calculated in the critical solder interconnects for different isothermal mechanical testing temperatures (22°C, 75°C, 100°C and 125°C) and the results are compared with the simulation results of different TC test conditions. This reliability determination with failure parameter isolation allows for improved integration with FEA modeling for a priori reliability prediction during the design process.

The increasing thermal demands in power electronic systems require the application of high temperature die attach materials. Transient Liquid Phase Sintered (TLPS) paste-based solder alloys have been demonstrated to effectively manage the thermal and mechanical load requirements of power modules. The microstructural features of these alloys provide interconnects with the necessary strength required to sustain high loads at high temperatures. To properly understand the influence of microstructure on mechanical behavior of these alloys, single lap shear experiments were performed on a TLPS system consisting of Copper and Tin particles (Cu-Sn). Nano-indentation measurements were performed on intermetallic phases of the TLPS, and the results obtained from lap shear testing and nano-indentation measurements are presented.

Fatigue failure of solder joints is one of the most common methods by which electronic packages fail. Electronic assemblies usually must cope with a temperature varying environment. Due to the mismatches in coefficients of thermal expansion (CTEs) of the various assembly materials, the solder joints are subjected to cyclic thermal-mechanical loading during temperature cycling. The main focus of this work is to investigate the changes in microstructure that occur in SAC305 and SAC+Bi lead free solders subjected to mechanical cycling. In this paper, we report on results for the SAC+Bi solder commonly known as SAC_Q or CYCLOMAX. Uniaxial solder specimens were prepared in glass tubes, and the outside surfaces were polished. A nanoindenter was then used to mark fixed regions on the samples for subsequent microscopy evaluation. The samples were subjected to mechanical cycling, and the microstructures of the selected fixed regions were recorded after various durations of cycling using Scanning Electron Microscopy (SEM). Using the recorded images, it was observed that the cycling induced damage consisted primarily of small intergranular cracks forming along the subgrain boundaries within dendrites. These cracks continued to grow as the cycling continued, resulting in a weakening of the dendrite structure, and eventually to the formation of large transgranular cracks. The distribution and size of the intermetallic particles in the inter-dendritic regions were observed to remain essentially unchanged.

With the larger size of Ball Grid Array (BGA) solder joints, the available volume for underfilling is significantly increased. Although the size of the solder joints and package dimension governs the volume of underfill material, the larger 2 nd level solder interconnects are more susceptible to thermal fatigue with certain underfills and thermal profiles. In this study, BGA packages were underfilled with two dedicated underfill materials and two soft materials used as conformal coatings and encapsulants in electronic products. Each of the selected materials was subjected to two thermal profiles, one with low mean temperature and a second with a high mean temperature. The variation in mean cyclic temperature demonstrates the influence of temperature dependent behavior of each underfill material on the loads solder joints experience in a BGA package. Material characterization was performed on the package and underfill materials and incorporated into finite element models. The influence of underfill material glass transition temperature (T g ) was found to be a critical factor on fatigue endurance of solder interconnects. Fatigue crack orientation within solder joints were found to be aligned with axial (normal) direction for BGAs with high CTE underfill materials. Simulations determined the magnitude of axial loading associated with each underfill material properties responsible for reducing fatigue life. The results developed in this paper reveal the factors associated with reduced fatigue endurance of certain underfill materials under temperature profiles with mean temperature conditions and contribute to the development of new criteria of underfill material selection for 2 nd level interconnects.

Wafer Level Chip Scale Package (WLCSP) has been a favorable packaging solution for compact portable consumer electronics. The microelectronics industry introduced Extra Low K (ELK) to enhance electric performances with the cost of diminishing mechanical reliability. The ELK itself and its interfaces are highly fragile and susceptible to fracture. ELK cracking under bumps and ELK inter layer delamination (ILD) from die corners are often observed during and after solder reflow and qualification process such as accelerated thermal cycling (ATC). In this study, the underfill selection and its fillet formation influence to the Chip Packaging Interactions (CPI) of WLCSP was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical interactions between die corner and underfill was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned WLCSP die corner subjected to thermal loading from 25°C to 125°C. The results clearly show captured deformations of die corner area under thermal loading. For the fillet formation influence, it shows that the high underfill fillet configuration gives higher normal strain at the die corner area during thermal cycling. For the underfill selection, it clearly shows that the strain difference at corner solder during thermal cycling caused by two different type of underfill material. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties and fillet height were performed on the ELK reliability of WLCSP. Energy release rate of the die corner crack were obtained and used as damage indicators for die corner ELK delamination.

The study of solder joint reliability is one of the priority issues in electronic packaging. Solder alloys experience a highly nonlinear material behavior when subject to thermal cycling. It is a time consuming and difficult task to study the behavior of solder joints using experimental approaches. Finite element analysis provides a more efficient way to better understand the behavior of solder joints when accurate material models are available. With the developments of FEA algorithms and computer resources, the analysis approaches used for electronic packaging assemblies have evolved from 2-dimensional to 3-dimensional analyses, with far fewer assumptions needed in the fully 3D case. In this paper, we compare different FEA approaches covering various 2D and 3D modeling techniques to understand their advantages and drawbacks, especially as related to simulation accuracy and efficiency. Several models for a typical BGA assembly were prepared and analyzed including traditional mesh continuity models (2D slice model, 3D slice model, and 3D quarter model), as well as advanced models that employ Multi-Point Constraints (MPCs) and submodeling (global/local models). The Anand viscoplastic model was used for the solder joint material behavior in all of the FEA approaches. For the 3D mesh continuity models, an optimal analysis approach has been proposed to achieve the best balance between the accuracy of the simulation result and numerical efficiency of the simulation. Mesh transitions were used to maintain mesh continuity between regions of different mesh densities. A best choice of load step size was also found to reduce overall simulation time. For the analysis using MPCs to to bond different meshes, two improved modeling strategies have been proposed including a suggested ratio of contacting elements and the use of multiple-MPC contact pairs to reduce overall mesh density of the FE model. An improved simulation simulation strategy using submodeling has also been developed to obtain the best compromise in the global and local models between the mesh quality and load step size. An improved geometric simplification of the solder joint for use with energy based fatigue criteria was developed. Finally, comparisons and suggestions were made for the best analysis approach when using FEA techniques to predict the behavior of solder joints in PBGA packages.

Lead free solders are renowned as interconnects in electronic packaging due to their relatively high melting point, attractive mechanical properties, thermal cycling reliability, and environment friendly chemical properties. The mechanical behavior of lead free solders is highly dependent on the operating temperature. Previous investigations on mechanical characterization of lead free solders have mainly emphasized stress-strain and creep testing at temperatures up to 125 °C. However, electronic devices, sometimes, experience harsh environment applications including well drilling, geothermal energy, automotive power electronics, and aerospace engines where solders are exposed to very high temperatures from 125–200 °C. Mechanical properties of lead free solders at elevated temperatures are limited. In this work, we have investigated the mechanical behavior SAC305 (96.5Sn-3.0Ag-0.5Cu) and SAC_Q (SAC+Bi) lead free solders at extreme high temperatures up to 200 °C. Stress-strain tests were performed on reflowed uniaxial specimens at four elevated temperatures (T = 125, 150, 175, and 200 °C). In addition, changes of the mechanical behavior of these alloys due to isothermal aging at T = 125 °C have been studied. Extreme care has been taken during specimen preparation so that the fabricated solder uniaxial test specimens accurately reflect the solder material microstructures present in actual lead free solder joints. High temperature tensile properties of the solders including initial modulus, yield stress, and ultimate tensile strength have been compared. As expected, our results show substantial degradations of the mechanical properties of lead-free solders at higher temperatures. With prior aging, these degradations become even more significant. Comparison of the results has shown that the addition of Bi to traditional SAC alloys improves their high temperature properties and significantly reduces their aging induced degradations.

Electronics in automotive underhood and downhole drilling applications may be subjected to sustained operation at high temperature in addition to high strain-rate loads. SAC solders used for second level interconnects have been shown to experience degradation in high strain-rate mechanical properties under sustained exposure to high temperatures. Industry search for solutions for resisting the high-temperature degradation of SAC solders has focused on the addition of dopants to the alloy. In this study, a doped SAC solder called SAC-Q solder have been studied. The high strain rate mechanical properties of SAC-Q solder have been studied under elevated temperatures up to 200°C. Samples with thermal aging at 50°C for up to 6-months have been used for measurements in uniaxial tensile tests. Measurements for SAC-Q have been compared to SAC105 and SAC305 for identical test conditions and sample geometry. Data from the SAC-Q measurements has been fit to the Anand Viscoplasticity model. In order to assess the predictive power of the model, the computed Anand parameters have been used to simulate the uniaxial tensile test and the model predictions compared with experimental data. Model predictions show good correlation with experimental measurements. The presented approach extends the Anand Model to include thermal aging effects.

Transient Liquid Phase Sintering (TLPS) is a novel high temperature attach technology. It is of particular interest for application as a die attach in power electronic systems because of its high melting temperature and high thermal conductivity. TLPS joints formed from sinter pastes are comprised of metallic particles embedded in matrices of Intermetallic Compounds (IMCs). Compared to conventional solder attach, TLPS joints contain a considerably higher percentage of brittle IMCs. This raises the concern that TLPS joints are susceptible to brittle failure. In this paper we describe and analyze the cooling-induced formation of vertical cracks as a newly detected failure mechanism unique to TLPS joints. In a power module structure with a TLPS joint as interconnect between a power device and a Direct Bond Copper (DBC) substrate, cracks can form between the interface of the DBC and the TLPS joint when large voids are located in the proximity of the DBC. These cracks do not appear in regions with smaller voids. A method has been developed for the three-dimensional modeling of paste-based TLPS sinter joints that possess complex microstructures with heterogeneous distributions of metal particles and voids in IMC matrices. Thermo-mechanical simulations of the post-sintering cooling process have been performed and the influence of microstructure on the stress-response within the joint and at the joint interfaces have been characterized for three different material systems (Cu+Cu 6 Sn 5 , Cu+Cu 3 Sn, Ni+Ni 3 Sn 4 ). The maximum principal stress within the assembly was found to be a poor indicator for prediction of vertical crack formation. In contrast, stress levels at the interface between the TLPS joint and the power substrate metallization are good indicators for this failure mechanism. Small voids lead to higher joint maximum principal stresses, but large voids induce higher interfacial stresses, which explain why the vertical cracking failure was only observed in joints with large voids.

The coarse heterogeneous microstructure of SAC alloys makes the behavior of interconnections highly sensitive to its geometric length-scale. Heterogeneous integration and the resulting increase in package complexity and miniaturization are making this scale-effect ever more important. This scale effect derives from the anisotropy of tin and the coarse multi-tiered microstructural heterogeneities in SAC solders. As a result, no two joints behave the same and every joint is unique depending on its specific microstructure. Product teams responsible for reliable heterogeneous integration have to ensure that they have adequate methods to deal with this variability. This paper highlights the multi-tiered microstructural morphology in SAC solders due to the solidification and crystallization process. At the highest tier in the joint microstructure are individual (highly anisotropic) grains that can be 100s of microns in size. At the next lower tier the primary heterogeneity is due to individual dendrites of pro-eutectic β tin, that can have lobes as large as 10–20 microns. At the next lower tier the characteristic heterogeneity is a eutectic mix of nanoscale Ag 3 Sn IMC particles dispersed in a Sn matrix. Researchers have long recognized that the grain morphology is extremely important to mechanical behavior of BGA solder joints because they are coarse-grained (i.e. there may be only a few anisotropic grains in each BGA solder joint). However, heterogeneous integration has now led to joints that are much smaller (less than 100 microns tall), thus making them of the same length-scale as individual tin dendrites within each grain. In other words, there may be just a few dendrites through the thickness of the joint. Unfortunately, very little attention has focused on SAC behavior at such a small length-scale. This study focuses on the effect of the tin-dendrite morphology on the effective behavior of SAC solder joints, using a combination of experiments and multi-tiered anisotropic models that combine dislocation nano-mechanics with composite micromechanics. The volume fraction of β-Sn dendrite within one crystal could vary from 20% to 80%, depending on the time and temperature above the liquidus temperature and the cooling rates. The effects of volume fraction and aspect ratio of Sn dendrites on the anisotropic steady-state creep rate of single crystal SAC specimen are examined. The objective of the study is to provide insights into the role that solder microstructural heterogeneity will play on package reliability in heterogeneous integration.

Current trends in the automotive industry point to increasing role of electronics for vehicle control, safety, efficiency and entertainment. Examples include lane-departure warning systems, collision avoidance systems, vehicle stability systems, and drive assist systems. Many of the automotive electronics systems are located under the hood of the vehicle mounted directly on engine or on transmission with sustained exposure to temperatures greater than 150°C in conjunction with vibration. Solder joint fatigue is a dominant failure modes under high-temperature vibration. Industry migration to lead-free solders has resulted in a proliferation of a wide variety of solder alloy compositions many of which are based on formulation of Sn, Ag and Cu. While it is well known that solder interconnects, accrue damage much faster when vibrated at elevated temperatures, the models for assessment of life under simultaneous temperature and vibration are scarce. State-of-art reliability models for solder joints focus on single stresses of vibration or thermal cycling. There is need for models for evaluating the survivability of leadfree solder assemblies to ensure 10-years, 100,000 miles life in automotive environments. In this paper, a new model has been proposed for life prediction of electronics under simultaneous temperature-vibration.

Predominant high melting point solders for high temperature and harsh environment electronics (operating temperatures from 200 to 250°C) are Pb-based systems, which are being subjected to RoHS regulations because of their toxic nature. In this study, high bismuth (Bi) alloy compositions with Bi-XSb-10Cu (X from 10 wt.% to 20 wt.%) were designed and developed to evaluate their potential as high-temperature, Pb-free replacements. Reflow processes were developed to make die-attach samples made out of the cast Bi alloys. In particular, die-attach joints made out of Bi-15Sb-10Cu alloy exhibited an average shear strength of 24 MPa, which is comparable to that of commercially available high Pb solders. These alloy compositions also retained original shear strength even after thermal shock between −55°C and +200°C and high temperature storage at 200°C. Brittle interfacial fracture sometimes occurred along the interfacial NiSb layer formed between Bi(Sb) matrix and Ni metallized surface. In addition, heat dissipation capabilities, using flash diffusivity, were measured on the die-attach assembly, compared to the corresponding bulk alloys. The thermal conductivity of all the Bi-Sb alloys was higher than that of pure Bi. By creating high volume fraction of precipitates in a die-attach joint microstructure, it was feasible to further increase thermal conductivity of this joint to 24 W/m·K, which is three times higher than that of pure Bi (8 W/m·K). Bi-15Sb-10Cu alloy has so far shown the most promising performance as a die-attach material for high temperature applications (operated over 200°C). Hence, this alloy was further studied to evaluate its potential for plastic deformation. Bi-15Sb-10Cu alloy has shown limited plastic deformation in room temperature tensile testing, in which premature fracture occurred via the cracks propagated on the (111) cleavage planes of rhombohedral crystal structure of the Bi(Sb) matrix. The same alloy has, however, shown up to 7% plastic strain under tension when tested at 175°C. The cleavage planes, which became oriented at smaller angles to the tensile stress, contributed to improved plasticity in the high temperature test.

Solder interconnects in electronic assemblies are susceptible to failures due to environmental high strain rate impact and cyclic stresses. To mitigate the failures, adhesive bonds can be added after the solder assembly process to provide additional mechanical support. For ball grid array (BGA) packages, the adhesive is normally applied to the corners of the package and referred to as corner staking. In addition to corner staking, underfill is also a strategy used to mitigate the stresses on the solder joints. While components with underfill has been widely studied, the study of the impact of corner staking on the reliability of packages remains limited. This paper presents a study of corner-staked BGA packages with tin-3.0 silver-0.5 copper (SAC305) solder subjected to temperature cycling. Experimental temperature cycling is conducted to examine impact of the selected corner staking material on the fatigue life of BGAs. Further, finite element analysis is conducted to understand the influence of material properties of staking material on the fatigue life of BGAs. The result of the study indicates that the presence of corner staking, with selected material properties, reduces the damage on the solder joints under thermal cycling, and thus increases its fatigue life by about 80%. This paper may serve as a guidance for staking material selection to improve the fatigue life of solder joints of BGAs under thermal cycling.

Most of the electronic devices manufactured are used in daily life and with the miniaturization process of these devices, in the day to day life there is a risk of drop impact failure. It has been important to analyze and ensure the reliability of any electronic devices under every type of loading. Drop impact is not only loading that can affect reliability, but the simultaneous thermal load, moisture, convection is also acting. Smaller devices like cell phones, laptops, tablets are more prone to accidental impact loads which create board interconnects failure by frequent drop occurrence. Therefore, a multi-dimensional approach is taking place in research to study product reliability. In this paper, comprehensive study of drop and shock test is done on Quad Flat No-lead (QFN) package board of two different thickness. The computation setup is done with thermal analysis by providing power to die of the package which creates non-uniform temperature distribution during the drop testing analysis. This way drop test is coupled with a thermal load which is more realistic analysis. Our study depends on young’s modulus, density, CTE, thermal conductivity, specific heat and Poisson’s ratio of the material. Therefore, Experimental work includes material properties characterization of two boards to get temperature dependent Coefficient of thermal expansion, poison’s ratio and young’s modulus values using Thermal mechanical analyzer (TMA), the Dynamic mechanical analyzer (DMA) and Universal testing machine. Finite element analysis (FEA) method is used for computational analysis. Effect of impact loading for two boards has been done to investigate board and solder joint reliability due thickness and layer stack-ups in PCBs in environmental condition and at elevated temperature. For computational analysis, the assembly is subjected to the drop test per JEDEC standards. [12] The main purpose of this work is to study the impact of drop test with the powered package and how the reliability of any assembly changes with changing the stiffness of printed circuit board. The comparison of the boards has been made to understand the effect of PCB layer stack-ups, thickness, and temperature effect on the reliability of solder interconnects by considering the stress-strain generation that is induced in the PCBs during the drop test.

The reliability assessment of package assembly is important to predict the performance of any microelectronic devices. Formation of fatigue cracks at the interface between the solder joint and component is the common failure occur in widely used microelectronic devices. Lead-free solders and advanced silicon process nodes with ultra-low-k (ULK) dielectrics flip chip package are used and are facing significant reliability challenges. The ultra-low-k materials improve performance by reducing parasitic capacitance and crosstalk between adjacent metal lines. [2] With low modulus, lower fracture toughness, higher coefficient of thermal expansion (CTE) and poorer adhesion of ultra-low-k material, when it is compared to the common dielectric materials, it becomes a major concern to analyze thermomechanical failures. From our past study, it has been concluded that solder joint reliability (SJR) of the small package depends on the copper content in the printed circuit boards (PCB). Also, the wire bond large PBGA packages are a cost-effective package with a substantial number of solder balls. The substrate and PCB have its impact on the solder ball, the mismatch in CTE of different components cause solder failure. In this paper, critical attention has been given to the copper content present in the PCB of different thicknesses and how PCB thickness is related to SJR. The structure of package plays a vital role in deciding reliability of package, as the different structure can shift stress point or distribute stresses to one or more components. The substrate or PCB stack-up or composition can strongly affect the package life. Many parameters need to be studied and package to substrate ratio is one of its which is discussed in this work. Material characterization of PCB with different thickness has been done. Thermal Mechanical Analyzer (TMA) is leveraged to measure temperature-dependent CTE, Dynamic Mechanical Analyzer (DMA) and Universal testing machine are used for measuring Elastic modulus and Poisson’s ratio. Further, a package assembly for the PCB of different thickness has been a model using ANSYS Workbench 18.0.

To solve the low-k delamination in chip assembly for high-end servers, our hypothesis is proposed that the low-k stress is determined by the bending moment and the stress relaxation of a joint. In our hypothesis, the low-k stress decreases as the joint height (SnAg bump height) becomes shorter, such as below 80μm, in 150μm-pitch joints. Our hypothesis is supported by simulation, in which the low-k stress is investigated as a function of the joint height, the joint material and also the joint width (the joint pitch). Finally, experiments are performed to evaluate the low-k delamination as a function of the joint height and our hypothesis is also supported by experiments.

Wide bandgap (WBG) semiconductors are revolutionizing the world of power electronics. They have the potential to bring about an unprecedented increase in power density. The ability to switch at ultrafast rates, coupled with the promise of high temperature operation, make these devices extremely desirable. However, having superior semiconductor devices will not automatically translate to superior package characteristics. In real applications, the performance of a power device is only as good as the package allows. One of the major drawbacks plaguing contemporary power modules is the wire-bonded interconnection. Wire bonds offer a high parasitic inductance. This paper presents a novel wire bondless SiC power MOSFET packaging technique. A commercially available bare die was reconfigured into a chip-scale package. The new form factor enabled the MOSFET to be bonded to a patterned FR4 substrate using flip-chip bonding. The electrical interconnection between the package and the substrate was established using solder balls — thus eliminating the requirement for wire bonds. The motivation for using a wire bondless method was a reduction in stray parasitic inductances and an increase in the thermo-mechanical reliability. Lower parasitic inductances will facilitate high switching frequencies which will promote miniaturization, a reduction in electromagnetic interference (EMI), and lead to lower switching losses. The proposed approach was demonstrated to reduce the parasitic loop inductance by a fctor of > 3× as compared with wire bonded modules.

Flexible electronics have a myriad of potential applications in fields such as healthcare, soldier situational awareness, soldier rehabilitation, sports performance, and textile manufacturing among other areas. The primary benefits that flexible electronics provide to both the producers and consumers are their light weight, low power consumption, efficiency, low cost of production, flexibility, and scalability. In comparison to rigid electronics, these systems would be subjected to a greater amount of mechanical and thermal stress in real-time due to their ability to be flexed, rolled, folded, and stretched. Environmental conditions such as bending, mechanical shock, water immersion, sweat, UV radiation, and temperature exposure could degrade the performance of these embedded electronic systems. At this time, there is a lack of suitable test standards and reliability data about flexible electronics manufacturing, assembly, and real-time use. In this paper, a fully flexible medical electronics system was built in full dimension to study the assembly and operation-related failure mechanisms of flexible and wearable electronics. The fabricated flexible electronics system measures pulse and muscle activity, and then transmits this data to a paired mobile device. The pulse rate was measured using an LED and a photo diode, while an electromyography (EMG) sensor was used to measure muscle activity. After collecting the data, the microcontroller sends it to a Bluetooth module, which can in turn transmit this information to a paired mobile device. Through experimentation with the fabricated flexible electronics device, unexpected degradation and quality issues were observed. In flexible PCBs, the space between the IC lead could not be isolated by the solder mask because of its large feature size and as a result, increases the risk of shortage between IC leads when subjected to mechanical stress. In addition, during the assembly process, high reflow temperature was found to subject a huge thermal stress on the connections between the solder pad and copper trace. Proper support of the solder pad should be designed to compensate the thermal stress during the reflow process, and prevent the copper joint on top of the board from being damaged. A set of guidelines for flexible medical electronics and an implementable reliability test standard can, therefore, be established for medical device manufacturers based on these reliability assessments.