Abstract In this technical paper, design, analysis and comparison of insulated metal substrates for high power wide-bandgap semiconductor-based power modules is discussed. The paper starts with technical description and discussion of state-of-the-art direct bonded copper substrates with different ceramic insulators such as AlN, Al 2 O 3 and Si 3 N 4 . This is followed by introduction of insulated metal substrates, material properties and options on each layer, and design approach for high power applications. The properties of dielectric thickness, and impact on power handling capability of the substrate are discussed. Insulated metal substrate design approach for SiC MOSFET based power modules is presented. Finite element analysis-based characterization and comparison of different designs including steady-state and transient thermal response is presented. The results show that IMS is a promising alternative to DBC in high power modules with improved transient thermal performance. IMS provides flexible building structure with multi-layer stacking options and variable thicknesses at different layers.

Abstract Since the introduction of plated through holes and microvias into the electronics industry, the reliability and manufacturability of these interconnects have been of great concern to the board designers, specifically in automotive and semiconductor industries. The failure of these structures is one of the main causes of an open circuit in printed circuit boards (PCBs). Typically, single and staggered microvias are not the cause of the failures, therefore, only stacked microvias and plated through holes (PTHs) are considered and analyzed in this study. This study includes broad parametric studies, using the finite element method (FEM), to investigate the effect of different geometrical parameters on the reliability and manufacturability of the stacked microvias and plated through holes. A fully automated methodology is developed to 1) analyze complex PCB designs with thousands of microvias and plated through holes, 2) identify and mark configurations susceptible to failure, and 3) build and run finite element simulations on the marked configurations. In doing so, the PCB drill files are first parsed, and the configurations are binned into three main categories; stacked, staggered and PTH configurations. Then using the related nearest-neighbor algorithms and based on the parametric study results, the configurations prone to failure are identified. Finally, finite element models are generated and simulated under thermal loading for the identified configurations. The simulations results are post processed for both reliability (fatigue life prediction under thermal cyclic loading over PCB service life) and manufacturability (overstress due to thermal shock during solder reflow). The modeling results and predictions correlate well to the experimental results available in the literature.

In this paper, several methods suitable for real time on-chip temperature measurements of power AlGaN/GaN based high-electron mobility transistor (HEMT) grown on SiC substrate are presented. The measurement of temperature distribution on HEMT surface using Raman spectroscopy is presented. We have deployed a temperature measurement approach utilizing electrical I-V characteristics of the neighboring Schottky diode under different dissipated power of the transistor heat source. These methods are verified by measurements with micro thermistors. The results show that these methods have a potential for HEMT analysis in thermal management. The features and limitations of the proposed methods are discussed. The thermal parameters of materials used in the device are extracted from temperature distribution in the structure with the support of 3-D device thermal simulation. The thermal analysis of the multifinger power HEMT is performed. The effects of the structure design and fabrication processes from semiconductor layers, metallization, and packaging up to cooling solutions are investigated. The analysis of thermal behavior can help during design and optimization of power HEMT.

Thermal interface materials (TIMs), which transmit heat from semiconductor chips, are indispensable in today’s microelectronic devices. Designing superior TIMs for increasingly demanding integration requirements, especially for server-level hardware with high power density chips, remains a particularly coveted yet challenging objective. This is because achieving desired degrees of thermal-mechanical attributes (e.g. high thermal conductivity, low elastic modulus, low viscosity) poses contradictory challenges. For instance, embedding thermally conductive fillers (e.g. metallic particles) into a compliant yet considerably less conductive matrix (e.g. polymer) enhances heat transmission, however at the expense of overall compliance. This leads to extensive trial-and-error based empirical approaches for optimal material design. Specifically, high volume fraction filler loading, role of filler size distribution, mixing of various filler types are some outstanding issues that need further clarification. To that end, we first forward a generic packing algorithm with ability to simulate a variety of filler types and distributions. Secondly, by modeling the physics of heat/force flux, we predict effective thermal conductivity, elastic modulus and viscosity for various packing cases.

During the last few decades, the microelectronics packaging industry has moved into the 2.5D to 3D space for increased density, functionality, and speed. Similar concepts and ideas for developing 2.5D to 3D power electronics packaging are desired to achieve even greater efficiency and power density over conventional power electronics packaging methods. Wide-band gap (WBG) semiconductors, such as SiC and GaN, have accelerated the ability to shrink the volumetric size and weight of these power conversion systems, and thus improve overall power density metrics, due to their inherent high frequency, high temperature, and high voltage capabilities. WBG power semiconductor devices, with these attributes, thus make themselves excellent candidates for more aggressive packaging, compared to Si-derived packaging, in order to not only take full advantage of the WBG device ratings, but also to achieve high power densities of the overall power conversion systems. Already different/multiple power semiconductor devices are being combined by processing them together on the same die to boost electrical performance and increase power density. It can be assumed that further levels of integration will be sought after for the next levels of packaging to enable similar gains, especially with the advent of double side solderable die. The 3D stacking of die, components, and substrates creates the question of how well will each of these perform in close proximity to each other. This work focuses on the numerical simulation and experimental measurements to predict the temperature distribution of power converters built in a stacked fashion. Thermal models of a stacked power electronic switching unit — a silicon controlled rectifier and anti-parallel diode — are modeled under the assumption of equally sized die. Temperature field maps are generated for 20W to 250W of power dissipations across the power semiconductor die. Thermal models are then compared with matching experimental setups to observe the effect of switching unit placement attached to a given substrate on the die junction temperatures for various scenarios of thermal crosstalk. Results from this work are expected to aid in the development 2.5D to 3D power electronic packaging by predicting thermal performance of stacked, ultra-dense, WBG device -based packages.

With the growth of Internet-based services, data centers must deal with increasing data traffic. Load-balancing technologies can help data centers process data effectively and stably; however, the current load-balancing methods do not take into account the heat generated by servers. Excessive heat can increase the failure rate of IT devices and the energy consumption of air conditioning systems, both of which lead to higher data center maintenance costs. This paper aims to simultaneously increase the coefficient of performance (COP) of the data center’s air-conditioning equipment and decrease the semiconductor-based equipment failure rate. To do so — and, consequently, reduce the operation and maintenance costs — we propose a novel request distribution system based on server-temperature and evaluate the proposed system by creating a thermal model of a data center. As a result, it is suggested that using the proposed load-balancing method the semiconductor failure rate can be reduced by 32 % when compared with the common round-robin distribution method, and by 19 % when compared with a load-balancing method based on CPU utilization. Moreover, the COP of the air-conditioning equipment obtained with the proposed method is recognized to be higher than those obtained with either the round-robin or the CPU-utilization-based methods.

Silicon photonics has emerged as a scalable technology platform for future optotelectronic communication systems. However, the current use of SiO 2 -based silicon-on-insulator (SOI) substrates presents a thermal challenge to integrated active photonic components such as lasers and semiconductor optical amplifiers due to the poor thermal properties of the buried SiO 2 optical cladding layer beneath these devices. To improve the thermal performance of these devices, it has been suggested that SiO 2 be replaced with aluminum nitride (AlN); a dielectric with suitable optical properties to function as an effective optical cladding that, in its crystalline state, demonstrates a high thermal conductivity (∼100× larger than SiO 2 in current SOI substrates). On the other hand, the tuning efficiencies of thermally-controlled optical resonators and phase adjusters, crucial components for widely tunable lasers and modulators, are directly proportional to the thermal resistance of these devices. Therefore, the low thermal conductivity buried SiO 2 layer in the SOI substrate is beneficial. Moreover, to further improve the thermal performance of these devices air trenches have been used to further thermally isolate these devices, resulting in up to ∼10× increase in tuning efficiency. Here, we model the impact of changing the buried insulator on a SOI substrate from SiO 2 to high quality AlN on the thermal performance of a MRR. We map out the thermal performance of the MRR over a wide range of under-etch levels using a thermo-electrical model that incorporates a pseudo-etching approach. The pseudo-etching model is based on the diffusion equation and distinguishes the regions where substrate material is removed during device fabrication. The simulations reveal the extent to which air trenches defined by a simple etch pattern around the MRR device can increase the thermal resistance of the device. We find a critical under-etch below which no benefit is found in terms of the MRR tuning efficiency. Above this critical under-etch, the tuning efficiency increases exponentially. For the SiO 2 -based MRR, the thermal resistance increases by ∼7.7× between the un-etched state up to the most extreme etch state. In the unetched state, the thermal resistance of the AlN-based MRR is only ∼4% of the SiO 2 -based MRR. At the extreme level of under-etch, the thermal resistance of the AlN-based MRR is still only ∼60% of the un-etched SiO 2 -based MRR. Our results suggest the need for a more complex MRR thermal isolation strategy to significantly improve tuning efficiencies if an AlN-based SOI substrate is used.

Wide bandgap (WBG) semiconductors are revolutionizing the world of power electronics. They have the potential to bring about an unprecedented increase in power density. The ability to switch at ultrafast rates, coupled with the promise of high temperature operation, make these devices extremely desirable. However, having superior semiconductor devices will not automatically translate to superior package characteristics. In real applications, the performance of a power device is only as good as the package allows. One of the major drawbacks plaguing contemporary power modules is the wire-bonded interconnection. Wire bonds offer a high parasitic inductance. This paper presents a novel wire bondless SiC power MOSFET packaging technique. A commercially available bare die was reconfigured into a chip-scale package. The new form factor enabled the MOSFET to be bonded to a patterned FR4 substrate using flip-chip bonding. The electrical interconnection between the package and the substrate was established using solder balls — thus eliminating the requirement for wire bonds. The motivation for using a wire bondless method was a reduction in stray parasitic inductances and an increase in the thermo-mechanical reliability. Lower parasitic inductances will facilitate high switching frequencies which will promote miniaturization, a reduction in electromagnetic interference (EMI), and lead to lower switching losses. The proposed approach was demonstrated to reduce the parasitic loop inductance by a fctor of > 3× as compared with wire bonded modules.

Graphene has great potential for ultra-sensitive strain sensors applications due to its high mechanical strength and good compatibility with the traditional semiconductor process. In the current study, we investigated the effect of tensile and bending deformations on the electronic states of graphene nanoribbons (GNRs) using density functional theory (DFT) to clarify the underlying mechanism of the piezoresistive properties of graphene. It is found that the electronic structure of armchair graphene nanoribbons (AGNRs) is very sensitive to the tensile deformation. When a uniaxial tensile stress is applied to AGNRs with width N a = 10, the band structure is modified, leading to the change in band gap approximately from 0 eV to 1.0 eV. The band gap values of bent AGNRs decrease significantly when the maximum local dihedral angle exceeds a critical value due to the orbital hybridization. Based on these knowledge, we fabricated a strain sensor using the graphene film grown by thermal chemical vapor deposition (CVD) method on Cu foil. The strain sensor is fabricated directly on the graphene-coated Cu foils by using the standard photolithography process and reactive ion etching (RIE) and then transferred onto a stretchable and flexible polydimethysiloxane (PDMS) substrate. The one-dimensional tensile test and three-dimensional bending test are performed to investigate the piezoresistive properties. A gauge factor 3.4 was achieved under the tensile deformation. The fabricated strain sensor also exhibits good performance to detect bending deformation.

We demonstrate the first contact resistance measurements of graphene–galinstan (g-g) ohmic contacts in an effort to improve the performance of graphene photonic devices. The nobility of carbon materials provide an interesting graphene sensor application to explore an oxidation free liquid metal - semimetal interface that can be used to lower contact resistance at source/drain terminals of a standard graphene phototransistor. Our methods utilize photopolymerization of the reactive monomer Trimethlylolpropane Triacrylate (TMPTA) in order to fabricate micro structures necessary to overlay liquid metal contacts on graphene. With the use of an industry standard transfer length method (TLM), a contact resistance of −124±28Ω was measured at both standard temperature and pressure. The results from our study suggest that liquid metals such as galinstan are comparable alternatives to rigid semiconductor interfaces and demonstrates interesting boundary characteristics that may lead to heavy chemical doping and associated low resistance contacts that are required to increase sensitivity in graphene photonic devices.

In this paper, we describe the system-level packaging of a 30 kW continuous, 55 kW peak, traction inverter to showcase the electro-thermal-mechanical performance enhancements of silicon carbide (SiC), a wide bandgap (WBG) semiconductor, over silicon. Higher efficiency, larger gravimetric and volumetric power densities, and smaller thermal management system requirements may be achieved through higher operating junction temperatures afforded by SiC versus silicon power devices. By applying advanced system-level packaging techniques, high-temperature control circuitry, utilizing 105°C-rated capacitors, and reducing the number of system interconnects and attaches to enable higher system reliability, a substantial cost reduction from the die level to the system level can be demonstrated by completely eliminating an electric vehicle’s secondary low-temperature cooling loop. The endgame is to reduce the traction inverter size (≥ 13.4 kW [peak]/L), weight (≥ 14.1 kW [peak]/kg), and cost (≤ $182/100,000) relative to output power while maintaining 15-year reliability metrics [1].

Recently two-dimensional layered semiconductors with promising electronic and optical properties, have opened up a new way for applications in atomically thin electronics and optoelectronics. Here we demonstrate large area synthesis of monolayer MoS 2 and WSe 2 using a chemical vapor deposition method at ambient pressure. The atomic analysis of the as-grown monolayer was conducted by spherical-aberration-corrected high resolution scanning transmission electron microscopy and atomic force microscopy. Raman spectroscopy was utilized to identify the monolayer configuration of the as-grown samples. Strong photoluminescence peaks at a visible wavelength were observed at room temperature in the as-grown monolayer samples. The mobility and carrier concentrations were calculated in as-grown monolayer-based transistor devices. The emergency of these two dimensional materials provides grand possibilities for future semiconductor device applications.

The convergence and miniaturization of computing and communications dictates building up rather than out. As planar device miniaturization continues to its ultimate limits, the complexity of circuit interconnections for 2-D devices becomes a limitation for performance and drives up power dissipation [1]. As the consumers demand more functions on their hand-held electronic devices, the need for more devices such as memory, CPU and GPU in hand-held type footprints is increasing. Chip-stacking (3-D) is emerging as a powerful tool that satiates such IC package requirements. A 3-D FPGA would overcome the interconnect limitations, resulting in greater silicon efficiency per function (number of used gates/total number of gates), faster signal/data throughput, and faster switching of the gate-level configuration. 3-D through-silicon-via (TSV) technology is being termed as the “ next big thing ” in the semiconductor arena and has the potential of revolutionizing the packaging industry but it has some inherent issues that need to be addressed before it could be implemented in the mainstream electronics industry. TSV fabrication process, thermal management of 3-D TSV packages, TSV joule heating, and chip package interaction (CPI), are some of the key issues in this technology [2, 3, 4, 5, 6]. In this paper, the thermo-mechanical chip-package-interaction (CPI) analysis is carried out and a full field compact 3D modeling methodology has been leveraged to assess the mechanical integrity of a 2 die 3D TSV package during attachment to substrate. This modeling methodology would provide damage predictions caused due to global and local CTE mismatch between the different package components. Mechanical interaction at the Si/TSV regions, back-end Cu/low-k stack, and the inter die μ-bumps during chip attachment is demonstrated in this paper.

Gallium arsenide is the second most used semiconductor material with applications in light-emitting diodes, field-effect transistors, and integrated circuits. Thus, understanding and controlling the thermal conductivity of gallium arsenide is crucial to design devices for such applications. The goal of this study is to predict the thermal conductivity of gallium arsenide as a function of temperature and vacancy concentration. Thermal conductivities are predicted using an equilibrium molecular dynamics method based on the Green-Kubo formalism with temperatures between 300 K and 900 K and vacancy concentrations up to 0.5%. Our results show that the thermal conductivities of the vacancy-free system predicted by our model are in good agreement with experimental values around the Debye temperature. In addition, our model predicts that conductivities significantly decrease with increasing vacancy concentration. At 300 K conductivities drop by 39.5% with a 0.1% defect content and 74.4% with 0.5% respect to that of the pure system. The power spectra of thermal conductivities and heat current autocorrelation functions indicate that phonon scattering produced near the vacancies reduces the contribution of the acoustic frequencies. The density of states quantifies the decrease of acoustic and optic frequencies by increasing the vacancy concentration.

Sn-Ag-Cu solder materials have been widely used for the mount process of electronics devices or semiconductor packages on print circuit board (PCB). The solder joints are sometimes opened under thermal cyclic loads as low cycle fatigue phenomenon. The fatigue life of solder joint has been investigated by many researchers with experimental and numerical methods. Generally, the induced thermal stress in solder joints should be relaxed as soon and creep damage is considered to be ignored in order to estimate lives of joints. However, it is probable that long term stress is applied to solder joints by the elastic follow-up phenomenon which are depending on the stiffness ratio between solder joints and the electronics device, because the elastic strain in PCB or the electronics device shifts to creep strain in solder joints gradually during a long time. Then the creep damage of solder joint should be counted for the mechanical design of mounted PCBs. And it is known that the interaction between creep damage and fatigue damage significantly shorten the life. In this study, it was discussed whether the interaction between fatigue damage and creep damage has to be considered or not for the mechanical design of the lead free solder joint with basic creep-fatigue tests at an elevated temperature.

3D packaging technology and TSV (Through Silicon Via) technology have been developed to reduce size and improve performance of semiconductor devices. On the other hand, cooling performance is decreased because thermal sources are accumulated and concentrated by chip stacking. In particular, unsteady thermal loads by hot spot, which is steep temperature elevation within a local area, produce damage in stacked semiconductor chips. In this study, temperature elevation in stacked chips and stresses around TSV structure in 3D SiP (Three Dimensional System in Package) are discussed with a large scale and a parallel computing simulator, which was based on FEM (Finite Element Method), under unsteady thermal conditions as hot spot. The level of heat generation was varied and conditions for device operation were suggested. In addition, stresses of Cu-TSV and Si chips are discussed as function of level of heat generation by hot spot to ensure the reliability of 3D SiP.

The increasing price of gold has resulted in industry interest in use of copper as alternative wire bonds interconnect material. Copper wire has the advantages of the lower cost, lower thermal resistivity, lower electrical resistivity, higher mechanical strength and higher deformation stability over the gold wire. In spite of the upside above, the Cu-Al wire bond is susceptible to the electrolytic corrosion and the reliability of Cu-Al wire bond is of great concern. Typical electronic molding compounds are hydrophilic and absorb moisture when exposed to humid environmental conditions. EMC contain ionic contaminants including chloride ions as a result of the chemical synthesis of the subcomponents of the resin, etching of metallization and the decomposition of the die-attach glue. The presence of moisture in the operating environment of semiconductor package makes the ion more mobile in the EMC. The migration of chloride ions to the Cu-Al interface may induce electrolytic corrosion inside the package causing degradation of the bond interface resulting in eventual failure. The rate at which the corrosion happens in the microelectronic packages is dependent upon the rate at which the ions transport through the EMC in addition to the reaction rate at the interface. In this effort, a multiphysics model for electrolytic corrosion in the presence of chloride has been presented. The contaminant diffusion along with the corrosion kinetics has been modeled. In addition, contaminated samples with known concentration of KCl contaminant have been subjected to the temperature humidity conditions (130°C/100RH)The resistance of the Cu-Al interconnects in the PARR test have been monitored periodically using resistance spectroscopy. The diffusion coefficients of chloride ion at various temperatures in the molding compound have been measured using inductively coupled plasma. Measured diffusion coefficients have been incorporated into the COMSOL multiphysics model. Moisture ingress into the EMC has been quantified through measurements of the weight gain in the EMC. Predictions from the COMSOL multiphysics model have been correlated with experimental data.

Coefficient of thermal expansion (CTE) characteristic of organic materials for substrates in flip chip package application demanded by semiconductor package requirements is becoming lower than ever. In general, height restrictions are imposed on package-on-package (PoP) devices in mobile applications. One should hence establish a tight budget on the height variation in manufacturing of the devices. Given such background, a lowering of the CTE characteristic of package substrates is an attractive solution for reducing package deformation upon manufacturing, since it contributes to minimize CTE mismatch of the substrates with silicon chips. In large-die flip chip applications such as high-end processors, a lower CTE substrate can mitigate mechanical stress not only on low-k layers in back end of the line (BEOL) underneath the chip bumps, but also on underfill layers during thermal cycling. Therefore an introduction of lower CTE materials in organic substrates is becoming essential for future applications of electronic devices. In this paper, thermal deformation behaviors of organic substrates associated with lowering of the CTEs of their constituent materials are analyzed by finite element analysis (FEA). The analyses are done on a 3-2-3 build-up layer structure substrate in order to focus onto typical application specific integrated circuit (ASIC) products. A finite element model for a test substrate is constructed by a method in which the substrate is divided into sections according to its circuitry patterns so that the lateral inhomogeneity of mechanical property is taken into account. The finite element analyses using the model showed that the package warpage decreases with lowering of the effective CTE of the substrate, but the warpage of the substrate itself increases and its surface profile changes from a concave shape to a convex shape. The analysis result of substrate warpage variation with the build-up material’s CTE showed that the selection of build-up materials with appropriate material properties can contribute to reduce the substrate warpage. The analysis also showed that the adverse impact to the substrate’s CTE reduction by such material selection is limited.

Electroplated copper thin films have started to be employed as the interconnection material in TSV structures of 3D semiconductor modules because of its low electric resistivity and high thermal conductivity. However, electrical and mechanical properties of electroplated copper thin-films have been found to vary drastically depending on their microtexture. In particular, the crystallographic quality (crystallinity) of grain boundaries in the electroplated copper thin-films plays an important role on the variations of these properties and the long-term reliability of the interconnections. This is because grain boundaries are the area where the atomic alignment of mateerials is disordered and thus, various defects such as vacancies, dislocations, impurities, and strain easily concentrate around them. This disorder of the atomic alignment causes the increase in the electrical resistivity, diffusion constant along the grain boundaries, and the brittleness of the material. Therefore, it is very important to evaluate the characteristics of a grain boundary quantitatively in order to control and assure the properties of the electroplated copper thin films. In this study, a novel tensile test method that can measure the strength of a grain boundary has been developed by using a focused ion beam system. In order to investigate the effect of the crystallinity of grain boundaries on their strength, an electron back-scatter diffraction method (EBSD) was employed for the quantitative characterization of grain boundaries. It was confirmed that the strength of grain boundaries with low crystallinity was much lower than that with high crystallinity.

There is an urgent need in surface mount technology (SMT) for a nontoxic, reusable and low temperature bonding technique which can afford good mechanical support as well as electrical contact. Meanwhile in the nanotechnology, many excellent and unique structure-related properties such as the high mechanical strength, the high conductivity and the adhesion ability of gecko feet have been studied. Our lab proposes a new patterned structure of Au nanowire array named nanowire surface fastener (NSF), which cold bonding for surface mount technology can be realized at room temperature. Then various methods have been developed to fabricate nanowire, such as arc discharge, catalytic CVD growth and template synthesis, and so on. Among these methods, the template method has been widely used for preparing one-dimensional nanostructures such as metals, semiconductors, polymers, and other materials by electrochemical, electroless deposition or sol-gel technique. Especially anodic aluminum oxide template assisted way has attached considerable attention due to its unique structure properties, such as controllable pore diameter, extremely narrow pore size distribution with high densities, high aspect ratios, and ideally cylindrical pore shape. The well arranged porous anodic aluminum oxide membrane is fabricated from aluminum film by two steps zM oxalic acid electrolytes. The anodic aluminum oxide membrane was investigated for features such as pore size, interpore distance, and thickness by 40 V. It is important for fabrication of porous anodic aluminum oxide template to find out elimination of the barrier layer of oxide and the pore extending rate by 0.5 M phosphoric acid. Morphologies of surface of aluminum film between anodization process and the anodic aluminum oxide barrier layer was researched by using atomic force microscope and scanning electron microscope. Results showed that the anodic aluminum oxide having the same diameter of the pore and the well arranged pore array without branching channel was obtained. The diameter of the pore before the pore extending treatment is 42 nm and the diameter of the pore after the pore extending treatment for 30 minutes is 86 nm. It was found that the diameter of the pore increased per 15 nm by the pore extending treatment for 10 minutes. We fabricated the through-hole anodic aluminum oxide template and made Cu nanowire by the template of our own making. By using Cu nanowire, we try to produce nanowire surface fastener and evaluate its properties.