Abstract Piezoresistive stress sensors have been shown to be a powerful tool for experimental evaluation of die stress distributions. Silicon Carbide (SiC) wide bandgap semiconductors are promising materials for development of high temperature power electronics. In the past, the analysis and design of stress sensors on silicon carbide have assumed that the wafer surface is aligned with the crystallographic axes. However, 4H silicon carbide wafers are produced with a four-degree off-axis cut to ensure high-quality homoepitaxial growth, so that the tilted wafer surface does not perfectly coincide with the fundamental crystallographic axis. Thus, the prior “on-axis” theory is an approximation, and errors in piezoresistive theory caused by such tilted wafer plane need to be discussed. These errors can affect both the results from calibration experiments as well as the stresses extracted during application of sensor rosettes. This paper discusses the theory and extraction of piezoresistive coefficients for 4H-SiC silicon carbide materials in the presence of off-axis starting wafers. Coordinate transformations for the piezoresistive coefficients are reviewed, the required direction cosines between the new rotated axes and the ideal axes are discussed, and the 6 × 6 matrix of piezoresistive coefficients (π-matrix) for the on-axis and off-axis cases are calculated. Many of the elements of the ideal on-axis π-matrixes are zero. In contrast, the off-axis is completely filled with non-zero values indicating additional coupling, particularly among the shear coefficients. Examples of the overall impact of these new terms on calibration and stress measurement are discussed.

Wafer Level Chip Scale Package (WLCSP) has been a favorable packaging solution for compact portable consumer electronics. The microelectronics industry introduced Extra Low K (ELK) to enhance electric performances with the cost of diminishing mechanical reliability. The ELK itself and its interfaces are highly fragile and susceptible to fracture. ELK cracking under bumps and ELK inter layer delamination (ILD) from die corners are often observed during and after solder reflow and qualification process such as accelerated thermal cycling (ATC). In this study, the underfill selection and its fillet formation influence to the Chip Packaging Interactions (CPI) of WLCSP was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical interactions between die corner and underfill was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned WLCSP die corner subjected to thermal loading from 25°C to 125°C. The results clearly show captured deformations of die corner area under thermal loading. For the fillet formation influence, it shows that the high underfill fillet configuration gives higher normal strain at the die corner area during thermal cycling. For the underfill selection, it clearly shows that the strain difference at corner solder during thermal cycling caused by two different type of underfill material. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties and fillet height were performed on the ELK reliability of WLCSP. Energy release rate of the die corner crack were obtained and used as damage indicators for die corner ELK delamination.

A DfR (Design for Reliability) approach which is systematically based on simulation, sensitivity analysis and experimental validation is applied for identifying, understanding and controlling the key factors which determine the solder joint reliability of eWLB (Embedded Wafer Level Ball Grid Array) packages that carry embedded 77 GHz dies and sit on hybrid PCB (Printed Circuit Board) stacks. The hybrid stack investigated in this work is characteristic to automotive RADAR (Radio Detection And Ranging) applications and consists of one low-loss RF (Radio Frequency) layer and several FR4 layers. In line with previous work [1], the mechanical material properties of the low-loss RF laminate material are found to be the key factor. Simulation is used to systematically screen for mechanical properties which are favorable for achieving a high solder joint reliability on the unconstrained PCBs used for standardized solder joint reliability testing. A simplified virtual assessment of PCBs constrained by the mounting in system module housings is done. Both simulation and experimental results show that RF laminate materials with low Young’s modulus are the class of materials which allows for the highest solder joint reliability for all the conditions investigated in this study.

In this study, the peeling process of UV-curable pressure sensitive adhesive tape from bump wafer is investigated through the use of finite element analysis, observation of high speed video, and actual wafer back-grinding process testing. In our experiment, a large deformation of adhesive is observed at the edge of bottom of bump, appearing on the side of the bump opposite tape-peeling direction when observed with high speed microscope video. The largely deformed adhesive creates a string shaped elongation. The adhesive residue is caused by the fracture of the adhesive string. We investigated how to generate the adhesive string in the tape-peeling process through the use of finite element analysis. In this analysis, a cohesive element is introduced into the adhesive layer. The analytical result shows the adhesive string at the same position of experiment and the stress distribution is different between the string part and the other area of adhesive. The influence of peeling angle and bump size is also investigated by the same finite element model. As a result, higher peeling angle and smaller bump sizes shows a shorter adhesive string, which lowers the risk of adhesive residue.

A key component of the MEMS cryogenic cooling systems we are developing is a MEMS compressor. Its function is to compress the refrigerants used in the cooling cycle. Layers of polyimide are stacked and patterned on a silicon wafer to create micro check-valves and a compression chamber over which a diaphragm is suspended. To achieve the high (4:1) pressure ratio needed for the refrigeration cycle, the polyimide diaphragm needs to be fabricated with minimal dead volume beneath it, hence the need for a sacrificial layer with thickness of 100–300 nm. The topography created by the check-valves and valve-seats makes atomic layer deposition (ALD) ideal due to its conformality. Furthermore, following sacrificial layer release, the inside of the compression chamber will also need to be coated with a hermetic moisture barrier layer to enable the device to operate at 4 atmospheres without leaking. ALD is therefore also ideal for the final internal coating because it does not require line-of-sight. Towards this end, we demonstrate here the concept of using ALD TiO 2 as a sacrificial layer to create a 5 mm × 5 mm × 20 m-thick polyimide membrane, suspended by ∼ 100–350 nm above a silicon wafer, followed by a second thinner ALD coating of the interior surfaces bounded by wafer and membrane. The air gap under the membrane, defined by the released sacrificial layer, was measured at about 130–370 nm using two independent methods: reflectometry, and FIB cross sectioning followed by SEM imaging of the air gap’s cross section. The membrane was removed from one chip and the thickness of the internal coating on the underlying silicon was measured with the reflectometer to be about 40 nm. We thus demonstrate the use of ALD TiO 2 as both a sacrificial layer for fabricating nanoscale gaps, as well as for coating nanoscale internal cavities and channels.

We demonstrate the Lid-Integral Silicon Coldplate topology as a way to bring liquid cooling closer to the heat source IC. It allows to eliminate one thermal interface material (TIM2), to establish and improve TIM1 during packaging, to use wafer-level processes, and to ease integration in 1st level packaging. We describe the integration, and analyze reliability aspects of this package using modeling and test vehicle builts. To compare the impact of geometry, materials and mechanical coupling on warpage, strains and stresses, we simulate finite element models of five different topologies on an organic LGA carrier. We measure the thermal performance in terms of thermal resistance from coldplate base to inlet liquid and obtain 15mm 2 K/W at 30 kPa pressure drop across the package. We build two different topologies using silicon coldplates and injection molded lids. Gasket-attached coldplates pass an 800 kPa pressure test, direct-attached coldplates fracture in the coldplate. The results advise to use a compliant layer between coldplate and the manifold lid and promise a uniformly thick TIM1 layer in the Si-Si matched topology. The work shows the feasibility of composite lids with integrated silicon coldplates in high heat flux applications.

We present the operation of capacitive micromachined ultrasonic transducers (CMUTs) in permanent contact mode as an efficient transducer. The gap height of our transducers is chosen to be slightly smaller than the static deflection of the plate due to the pressure difference between the ambient and the vacuum cavity. Thus, the plates are in contact with the bottom of the cavities even with no dc bias applied. The devices were fabricated based on the thick box process. High-temperature assisted direct wafer bonding technique was used to fabricate devices with such large cell size (radii ∼ 2000 μm) featuring low frequencies ∼100–150 kHz. Extensive acoustic characterization was performed to demonstrate the behavior of such CMUTs in terms of displacement profile, output pressure and acoustic pitch-catch response. A maximum sound pressure of ∼145 dB (SPL) at the transducer surface is measured at 240 V dc and 10 V ac with 100 cycles of burst signal. This is a great improvement from conventional CMUTs (with deeper gap height, operating at 55 kHz), which requires 350 V dc and 200 V ac in order to achieve an output pressure of 129 dB (SPL) at the transducer surface. The results presented in this paper demonstrate that operating CMUTs in permanent contact mode indeed enhances the device output pressure, and provides a good candidate for efficient ultrasonic transducers.

Microwave and power electronics based on GaN enables the performance of systems and their safe operating area to be driven to ‘extremes’. One of the major issues that then arises is thermal management. This includes heat transfer limitations across interfaces, however also the need of incorporating novel high thermal conductivity materials such as diamond. Thermal parameters of these novel device systems and their implications on the near junction temperature in the devices are not well known. The role of interfaces between the GaN transistor and the diamond substrate, and of the diamond thermal properties themselves near this interface are discussed, and novel thermal characterization approaches, such as enabling fast determination of the thermal resistance on the wafer level, as well as of lateral diamond thermal conductivity, are presented.

Ultrasound is increasingly in demand as a medical imaging tool and can be particularly beneficial in the field of intracardiac echocardiography (ICE). However, many challenges remain in the development of a 3D ultrasound imaging system. We have designed and fabricated a quad-ring capacitive micromachined ultrasound transducer (CMUT) for real-time, volumetric medical imaging. Each CMUT array is composed of four concentric, independent ring arrays, each operating at a different frequency, with 128 elements per ring. In this project, one ring will be used for imaging. A large (5mm diameter) lumen is available for delivering other devices, including high intensity focused ultrasound transducers for therapeutic applications or optical fibers for photoacoustic imaging. We address several challenges in developing a 3D imaging system. Through wafer vias are incorporated in the fabrication process for producing 2D CMUT arrays. Device integration with electronics is achieved through solder bumping the arrays, designing a flexible PCB, and flip chip bonding CMUT and ASICs to the flexible substrate. Finally, we describe a method for integrating the flex assembly into a catheter shaft. The package, once assembled, will be used for in-vivo open chest experiments.

During the fabrications of 2.5D and 3D advanced packages, the needs for intermediate thinning and planarization processes persistently exit. This paper highlights the attributes of successful implementations, i.e., increased performances and yields for these processes, which have been identified by the market requirements for a variety of applications. Different packages with different materials systems and product goals lead to different requirements. This paper includes the thinning and polishing of TSV wafers in bonded wafer pairs for Si IC devicess or interposers, the thinning of overmolded, reconstituted wafers in eWLB applications, and the planarizations of metal bumps and RDL features in PoP, CSP, or fine line-and-space (L/S) substrate fabrications.

Plasma dicing has rapidly gained traction as a viable alternative to conventional blade and laser techniques for wafer singulation. This has been due mostly to the significant benefits plasma dicing delivers in relation to the quality and reliability of devices singulated in this manner. Key to the successful integration of plasma dicing, into the established hierarchy of singulation techniques, is how the ancillary parts of the process flow can be utilized or adapted to accommodate it. More importantly, is the ease at which this can happen and also, how implementation can be achieved in a cost effective manner.

Recent electronic device packaging, for instance, CSP has a bonded structure of IC chip and polymers, and delamination occurs frequently at the interface between IC and a resin. Furthermore, thermal stresses which are caused by a temperature variation in the bonding process of CSP and heat cycles for environment temperature will influence on the strength of interface. In the present paper, the delamination test for specimens with different thicknesses of an interlayer is carried out to investigate the strength of multi-layered joints, and the critical value for the intensity of singularity at delamination of interface is determined through a numerical analysis using a boundary element analysis. In experiment, a silicon wafer is joined with a silicon-on-sapphire (SOS) plate by a resin. The SOS is composed of silicon film and sapphire plate. The joining strength in silicon, resin and SOS joints with a rectangular bonding area is investigated. The bonded specimens are prepared under different cooling rate. Load is applied to the specimen so as to delaminate at the interfaces of silicon film and sapphire. Delamination occurs at the interface between silicon film and sapphire plate in the specimen. Nominal stress for delamination is about 2.23–3.59 MPa. From a comparison of the strength of joint for rapid and slow cooling conditions, it is found that the residual stress reduces the strength of joint. In the numerical analysis, the intensity of singularity at the corner of interface for a unit load is determined. The intensity of singularity at the corner of the interface is related to the intensities of singularity in the radial direction and on the angle from the side free surface. The critical intensity of singularity for delamination of the interface is obtained by multiplying the force at delamination. Then, the critical intensity of singularity is determined as 168 MPa•mm 0.18 regardless of the thickness of silicon film.

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.

This paper reports the mechanical properties of single crystal silicon surface changed with hydrogen atoms trapped by underwater boiling treatment. Nanoindentaion test using a Berkovich indenter in six different indentation loads ranging from 100 μN to 1000 μN was conducted to obtain the load-displacement curve. The energy dissipated in plastic deformation, i.e. plasticity energy, during indentation on silicon wafers with different carrier concentration (undoped, lightly and heavily boron doped silicon) were compared. After boiling treatment, increment in the plasticity energy was observed on silicon containing boron. This result suggests that hydrogen atoms trapped inside silicon enhanced dislocation mobility leading to larger plastic deformation.

Laser drilling of silicon carbide (SiC) wafer in air (dry ablation) and underwater by using ns pulsed infrared (1064 nm) Nd: YAG laser is investigated. In order to suggest optimal parameters of via processing in SiC wafer, the effects of pulse number, laser fluence, water film thickness, and focus position are evaluated. As compared with dry ablation vias, decreasing etching rate, increasing via diameter, and generation of cracks in high-energy regime are observed in liquid-assisted processing. However, it is found that it can create vias without debris, HAZ, cracks. Also, optimal parameter set for infrared pulse laser processing under water is found to be the laser fluence of less than 10 J/cm 2 and water thickness of 1mm.

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place. In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability. In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.

Recent electronic device packaging, for instance, Chip size package (CSP) has a bonded structure of IC chip and polymers, and delamination occurs frequently at the interface between IC and a resin. Furthermore, thermal stresses which are caused by a temperature variation in the bonding process of CSP and heat cycles for environment temperature will influence on the strength of interface. In the present paper, the delamination test for specimens with different bonding areas and geometries is carried out to investigate the strength of multi-layered joints. In particular, a silicon wafer is joined with a silicon-on-sapphire (SOS) plate by a resin. The SOS is composed of silicon film, SiO 2 film and sapphire plate. The thicknesses of silicon film, SiO 2 film and sapphire plate are 0.45μm, 0.2μm, 600μm, respectively. The joining strength in silicon, resin and SOS joints with triangular and rectangular bonding area is investigated. The triangular and rectangular shape bonding areas are 3mm 2 and 12mm 2 , respectively. The bonded specimens are prepared under different cooling rate. Load is applied to the specimen so as to delaminate at the interfaces of SiO 2 film and sapphire. From the delamination test, it is found that residual thermal stress and the geometry of bonding area affect the strength of interface. In the case of the triangular area specimen, delamination occurs at the interface between SiO 2 film and sapphire plate in the silicon-resin-SOS specimen. The nominal stress for delamination is about 1.99MPa. In the case of rectangular bonding area specimen, delamination occurs at the interface between SiO 2 film and sapphire plate in the silicon-resin-SOS specimen. Nominal stress for delamination is about 2.23MPa. From a comparison of the strength of joint for rapid and slow cooling conditions, it is found that the residual stress reduces the strength of joint.

Through-silicon via (TSV) technology is expected to overcome the limitations of I/O density and helps in enhancing system performance of conventional flip chip packages. One of the challenges for producing reliable TSV packages is the stacking and joining of thin wafers or dies. In the case of the conventional solder interconnections, many reliability issues arise at the interface between solder and copper bump. As an alternative solution, Cu-Cu direct thermo-compression bonding (CuDB) is a possible option to enable three-dimension (3D) package integration. CuDB has several advantages over the solder based micro bump joining, such as reduction in soldering process steps, enabling higher interconnect density, enhanced thermal conductivity and decreased concerns about intermetallic compounds (IMC) formation. Critical issue of CuDB is bonding interface condition. After the bonding process, Cu-Cu direct bonding interface is obtained. However, several researchers have reported small voids at the bonded interface. These defects can act as an initial crack which may lead to eventual fracture of the interface. The fracture could happen due to the thermal expansion coefficient (CTE) mismatch between the substrate and the chip during the postbonding process, board level reflow or thermal cycling with large temperature changes. In this study, a quantitative assessment of the energy release rate has been made at the CuDB interface during temperature change finite element method (FEM). A parametric study is conducted to analyze the impact of the initial crack location and the material properties of surrounding materials. Finally, design recommendations are provided to minimize the probability of interfacial delamination in CuDB.

Submerged jet impingement boiling has the potential to enhance pool boiling heat transfer rates. In most practical situations, the surface could consist of multiple heat sources that dissipate heat at different rates resulting in a surface heat flux that is non-uniform. This paper discusses the effect of submerged jet impingement on the wall temperature characteristics and heat transfer for a non-uniform heat flux. A mini-jet is caused to impinge on a polished silicon surface from a nozzle having an inner diameter of 1.16 mm. A 25.4 mm diameter thin-film circular serpentine heater, deposited on the bottom of the silicon wafer, is used to heat the surface. Deionized degassed water is used as the working fluid and the jet and pool are subcooled by 20°C. Voltage drop between sensors leads drawn from the serpentine heater are used to identify boiling events. Heater surface temperatures are determined using infrared thermography. High-speed movies of the boiling front are recorded and used to interpret the surface temperature contours. Local heat transfer coefficients indicate significant enhancement upto radial locations of 2.6 jet diameters for a Reynolds number of 2580 and upto 6 jet diameters for a Reynolds number of 5161.

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.