Thermal Interface materials are crucial elements for packaging of power electronics. In particular, development of high temperature lead free die-attach thermal interface materials for silicon carbide wide bandgap power electronics is a challenge. Failures of power electronics package modules often occur at die-attach areas. Among major options, sintered silver shows advantages in ease of applications. Cost, reliability, and integration are concerns for technology implementation. The current study first discusses issues and status reported in literatures. Then it focuses on cost reduction and improvement of sintered silver using enhancement structures at micro and nano scales. A few design architectures are analyzed by finite element methods. The feasibility of strengthening edges and corners is also assessed. The downside of potential increase of unfavorable stresses to accelerate void coalescence would be discussed in conjunction with design concept of power electronics package modules for paths of solutions in the form of integrated module systems.

As the automotive industry shifts towards the electrification of drive trains, the efficiency of power electronics becomes more important. The use of silicon carbide (SiC) devices in power electronics has shown several benefits in efficiency, blocking voltage and high temperature operation. In addition, the ability of SiC to operate at higher frequencies due to lower switching losses can result in reduced weight and volume of the system, which also are important factors in vehicles. However, the reliability of packaged SiC devices is not yet fully assessed. Previous work has predicted that the different material properties of SiC compared to Si could have a large influence on the failure mechanisms and reliability. For example, the much higher elastic modulus of SiC compared to Si could increase strain on neighboring materials during power cycling. In this work, the failure mechanisms of packaged Si- and SiC-based power devices have been investigated following power cycling tests. The packaged devices were actively cycled in 4.5 s heating and 20 s cooling at ΔT = 60–80 K. A failure analysis using micro-focus X-ray and scanning acoustic microscopy (SAM) was carried out in order to determine the most important failure mechanisms. The results of the analysis indicate that the dominant failure mechanism is wire bond lift-off at the device chip for all of the SiC-based devices. Further analysis is required to determine the exact failure mechanisms of the analyzed Si-based devices. In addition, the SiC-based devices failed before the Si-based devices, which could be a result of the different properties of the SiC material.

This paper firstly reviews the failure causes, modes and mechanisms of two major types of capacitors used in power electronic systems — metallized film capacitors and electrolytic capacitors. The degradation modeling related to these capacitors is then presented. Both physics-of-failure and data-driven degradation models for reliability and lifetime estimation are discussed. Based on the exhaustive literature review on degradation modeling of capacitors, we provide a critical assessment and future research directions.

Power output to electric traction drive systems varies over a wide range during real-world operation. As a result, the inverters, responsible for converting direct current battery (DC) to alternating current (AC) for electric motor operation, experience temperature changes that are important to consider in thermal design of the whole system, as well as implications for reliability in actual use. Because of the implications of temperature on device & system reliability, it is necessary to design appropriate thermal management systems to control their temperatures to meet product reliability goals. This study utilizes US Environmental Protection Agency standard driving schedules as case studies in how driving characteristics result in power module temperature profiles during operation for various heat removal schemes and design efficiencies. The temperature profiles obtained in this study clearly demonstrate a strong relationship between motor power output and inverter heat sink temperature. Moreover, when integrated with various degrees of road incline, the driving schedules show how road and elevation also impacts the need for various cooling technologies. This information can be integrated into use condition analyses for predicting reliability of the electronic components using reliability models developed from accelerated testing and qualifications to ensure the proper certification envelope is demonstrated for any given vehicle and environment, as well as demonstrate the effectiveness of cooling methods for determination of technical and economic feasibility.

In this study, we have conducted a combined numerical and experimental study on the Poisson’s ratio of SAC lead free solders. The Poisson’s ratio (PR) is one of the basic mechanical properties used in many material constitutive models. Although often not measured, it is important property in many finite element method (FEM) calculations. The value of the Poisson’s ratio of SAC lead free solders is relatively unexplored compared to other material properties, and for FEA simulations it is typically assumed to be v = 0.3. In the current work, we have shown the effects of the chosen value of the solder joint Poisson’s ratio on the finite element results for BGA components subjected to thermal cycling. In the finite element models, the reliability predictions were based on the Morrow-Darveaux energy-based fatigue model. Several sizes (5, 10, 15 mm) of PBGA components with SAC305 solder joints with 0.4 and 0.8 mm spacing were modeled. The packages were subjected to a time dependent cyclic temperature distribution from −40 to 125 °C. The package assemblies were assumed to be in a stress-free state at 25 °C (room temperature), with no residual stresses induced in the manufacturing process. The simulation results have demonstrated that for specified range of Poisson’s ratio values of 0.15 < v < 0.40, the solder Plastic Work varied over 20% and the Predicted Reliability Varied over 50%. To determine the actual Poisson’s ratio experimentally, uniaxial tensile stress-strain tests were carried out on SAC305 (96.5Sn3.0Ag0.5Cu) specimens using a micro tension/torsion testing machine with two strain rates (0.0001, and 0.00001 (sec −1 )), four testing temperatures (T = 25, 50, 75, 100 °C), and several durations of prior aging at T = 125 °C. Deformations and strains in axial and transverse directions were measured using strain gages with automatic data acquisition from LabVIEW software. The recorded transverse strain vs. axial strain data were then fit with a linear regression analysis to determine the Poisson’s ratio values. A test matrix of experiments was developed to study the effects of temperature, strain rate, alloy composition, and solidification cooling profile on the value of solder Poisson’s ratio. The Poisson’s ratio was found to increase with increasing temperature, and decrease with increasing strain rate. Using a slower solidification cooling profile led to an increase in the solder Poisson’s ratio value. Finally, the microstructural coarsening that occurs during isothermal aging lead to an increase in the Poisson’s ratio.

Flip chip (FC) packaging techniques in modern power electronics have enabled increased power density in module performance, but mechanical stresses induced by thermal expansion during inherent operating conditions in the power devices and packages create a need for understanding thermomechanical fatigue mechanisms that lead to reliability concerns. Moreover, in actual use, these mechanical stresses impact the reliable lifetime alongside thermal factors (such as diffusion and microstructural transformation) and other process history effects. This amalgam of damage inducing phenomena make development of a concise association between damage, fatigue, and stress factors difficult to determine. For reliability demonstration under fatigue loading, accelerated life testing (ALT), such as Thermal Cycling (TC), are commonly used in industry; however, long duration and expensive equipment required for TC limit its utility, especially when considering the high cost of wide-bandgap devices and modules, and the limitation of high temperature (> 150°C) testing standards. As a result, alternative test methodologies are needed to provide faster, cheaper, and design integrable reliability determination. In this work, an accelerated test methodology is introduced and designed to simulate these mechanical stresses at isothermal conditions, which is demonstrated using test chips that are analogous to power devices. By stressing these devices in a controlled environment, mechanical stresses become de-coupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device-relevant, flip-chip solder interconnects while monitoring cycles-to-failure (CTF). Also, Finite Element Analysis (FEA) is used to extract various damage metrics of different solder materials (including PbSn37/63, SAC305 and Nano-silver) in both thermal operation and the introduced alternative mechanical testing conditions. In doing so, test protocol translations to common qualification tests (or use condition thermal profiles) can be determined and are validated using the mechanical shear stress testing method. Plastic work density and maximum shear were calculated in the critical solder interconnects for different isothermal mechanical testing temperatures (22°C, 75°C, 100°C and 125°C) and the results are compared with the simulation results of different TC test conditions. This reliability determination with failure parameter isolation allows for improved integration with FEA modeling for a priori reliability prediction during the design process.

Active power cycling is a standardized and well-established method for reliability assessment and product qualification in power electronics technologies. Repetitive pulses of load current are applied to cause cyclic thermal swings in the p-n junction and in the whole semiconductor device. They induce thermo-mechanical stresses, which ultimately leads to the typical interconnect failure in the ‘devices under test’. However, these tests are insensitive with respect to new automotive system architectures, in which power electronics devices are exposed to additional loads besides the intrinsic thermal swings. The trends in power electronics towards miniaturization, higher power density, heterogeneous system integration, and the deployment of power electronics in harsher environments combined with longer lifetime and higher uptime requirements strongly increase the reliability demands in general and the need for more improved reliability assessment methodologies in particular. The new testing methods shall be more comprehensive and more efficient, i.e., they shall simultaneously cover the real service conditions better and reduce testing time. One promising approach is the combination of loading factors — such as the superposition of active power cycling by passive thermal cycles. Both loading factors are well-known to cause most relevant failure mechanisms in power electronics. In reality, the power electronic devices are exposed to both factors simultaneously. Hence, this load case should also be replicated in the test. The paper will report a systematic investigation of such superimposed test schemes, which cover the case of self-heating and passive heating (from neighboring elements) of the power electronics devices under real service conditions. Typical discrete power electronics components in TO-200 packages are selected as test vehicles as they are likewise relevant for the domains of consumer or automotive electronics. The paper details the test concept and discuss the quantitative and qualitative test results.

In this work, a low temperature method is proposed for the economical fabrication of three-dimensional (3D) ceramic substrate for Ultraviolet Light-Emitting Diodes (UV-LED) packaging. The 3D ceramic substrate using the inorganic alkali activated aluminosilicate cement paste (IAAACP) is molded by sacrificing the patterned wax mold. By controlling the viscosity, milling time, and curing temperature the of the IAAACP, the high strength 3D ceramic substrate is achieved, the corresponding shear strength reaches to 12.5MPa. After thermal shock and heat resistant test, the shear strength changed slightly, indicating the 3D ceramic substrate has excellent thermal reliability. These experimental results indicate that the prepared 3D ceramic substrate has a potential application for UV-LED packaging.

Sintered silver-based bonded interfaces are a critical enabling technology for high-temperature, compact, high-performance, and reliable wide-bandgap packages and components. High-pressure (∼40 MPa) sintered silver interfaces have been implemented commercially, most notably the commercial products offered by Semikron. To reduce manufacturing complexity, there is significant industry interest in pressure-less sintered silver interfaces. To this end, current formulations of sintered silver paste are comprised of purely nano-sized silver particles or a combination of nano- and micro-sized silver particles/flakes. It is essential to quantify the mechanical properties and determine the reliability of these interfaces prior to use in automotive power electronics applications. In this paper, research efforts at the National Renewable Energy Laboratory, in collaboration with Virginia Polytechnic Institute and State University and an industry partner, in optimizing the synthesis procedure and mechanical characterization of sintered silver double-lap samples are described. These double-lap samples were synthesized using pressure-less sintering techniques. Shear testing was conducted at multiple temperatures and displacement rates on these samples sintered using two types of sintered sintered silver pastes, one of them consisting of nano-silver particles and the other a hybrid paste or a combination of nano- and micron-sized silver flakes, employed in a double-lap configuration. Maximum values of shear stress obtained from the characterization study are reported.

Resistor reliability rules are defined by certain electrical parameters that depend on operating temperature. As shown by Black’s Equation, a temperature change of 5°C can lead to a 30% reduction in expected lifetime [1]. The temperature rise of a resistor depends on its dimensions and thermal properties as well as those of surrounding materials that separate the resistor from the heat sink. In this study, a modified approximate model based on Schafft’s equation is developed to estimate the operating temperature and assess the reliability of BEOL microresistor structures. The additional contribution of the substrate thermal resistance is added to the model and validated through a combined approach of experimental thermal mapping and numerical modeling. The developed analytical and numerical model are validated with the experimental temperature maps and could then be used for parametrization to aid the BEOL design process.

Nowadays microelectronic packaging has become a billion dollar business. Due to the increased material and production costs per package, manufacturing yield loss in this state-of-art business is expected to be at a bare minimum which is tough to persevere in a high volume manufacturing environment. Additionally, high performance and varied power computing needs in the electronic business demands microprocessors with different form factors and complex package designs. One of the most common joint which is extensively used in such a complicated package is the polymer to metal bonding. In the latest technology products involving high package warpage, interfacial bonding has to be strong enough to withstand the dynamic warpage and high mechanical stresses associated with it and hence the reliability of polymer to metal adhesion is critical. In this paper, fundamental mechanisms related to adhesion phenomena of polymer-metal interface are proposed. Adhesive failure modes related to polymer-metal bonding and key variables influencing the bonding of silicone based polymer material to nickel electroplated on copper in an integrated circuit heat spreader assembly are experimentally studied. Factors modulating polymer to metal bonding including interfacial chemistry, surface contamination and material roughness are evaluated.

Wafer Level Chip Scale Package (WLCSP) has been a favorable packaging solution for compact portable consumer electronics. The microelectronics industry introduced Extra Low K (ELK) to enhance electric performances with the cost of diminishing mechanical reliability. The ELK itself and its interfaces are highly fragile and susceptible to fracture. ELK cracking under bumps and ELK inter layer delamination (ILD) from die corners are often observed during and after solder reflow and qualification process such as accelerated thermal cycling (ATC). In this study, the underfill selection and its fillet formation influence to the Chip Packaging Interactions (CPI) of WLCSP was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical interactions between die corner and underfill was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned WLCSP die corner subjected to thermal loading from 25°C to 125°C. The results clearly show captured deformations of die corner area under thermal loading. For the fillet formation influence, it shows that the high underfill fillet configuration gives higher normal strain at the die corner area during thermal cycling. For the underfill selection, it clearly shows that the strain difference at corner solder during thermal cycling caused by two different type of underfill material. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties and fillet height were performed on the ELK reliability of WLCSP. Energy release rate of the die corner crack were obtained and used as damage indicators for die corner ELK delamination.

In power electronic, ceramic substrates are used owing to their high thermal conductivity and dielectric strength. These substrates cannot withstand high voltages in the range of 20kV because thickness limitations inherit from the direct bond copper manufacturing method. This manufacturing process uses high temperature in order to bond the material layers. This negatively affects the material’s reliability due to the differing materials thermal expansion coefficients and the resulting residual stress. All this results in hindering the ceramic substrate in obtaining a higher dielectric strength. In contrast, cold gas spray has the potential to provide higher reliability due to its bonding mechanism, which relies on plastic deformation of solid particles at very high strain rates during impact to create a mechanical bond, forming a thick deposit. However, cold gas spray on ceramics has not been widely studied due to their brittleness and their inability to form a metallic bond. This work is aimed at providing an effective processing parameter map of the cold gas spray process to achieve a thick copper deposit on aluminum nitride on the basis of the comparison of experimental results with a numerical model and finite element simulation formulated in Mathematica and ABAQUS, respectively.

The study of solder joint reliability is one of the priority issues in electronic packaging. Solder alloys experience a highly nonlinear material behavior when subject to thermal cycling. It is a time consuming and difficult task to study the behavior of solder joints using experimental approaches. Finite element analysis provides a more efficient way to better understand the behavior of solder joints when accurate material models are available. With the developments of FEA algorithms and computer resources, the analysis approaches used for electronic packaging assemblies have evolved from 2-dimensional to 3-dimensional analyses, with far fewer assumptions needed in the fully 3D case. In this paper, we compare different FEA approaches covering various 2D and 3D modeling techniques to understand their advantages and drawbacks, especially as related to simulation accuracy and efficiency. Several models for a typical BGA assembly were prepared and analyzed including traditional mesh continuity models (2D slice model, 3D slice model, and 3D quarter model), as well as advanced models that employ Multi-Point Constraints (MPCs) and submodeling (global/local models). The Anand viscoplastic model was used for the solder joint material behavior in all of the FEA approaches. For the 3D mesh continuity models, an optimal analysis approach has been proposed to achieve the best balance between the accuracy of the simulation result and numerical efficiency of the simulation. Mesh transitions were used to maintain mesh continuity between regions of different mesh densities. A best choice of load step size was also found to reduce overall simulation time. For the analysis using MPCs to to bond different meshes, two improved modeling strategies have been proposed including a suggested ratio of contacting elements and the use of multiple-MPC contact pairs to reduce overall mesh density of the FE model. An improved simulation simulation strategy using submodeling has also been developed to obtain the best compromise in the global and local models between the mesh quality and load step size. An improved geometric simplification of the solder joint for use with energy based fatigue criteria was developed. Finally, comparisons and suggestions were made for the best analysis approach when using FEA techniques to predict the behavior of solder joints in PBGA packages.

Lead free solders are renowned as interconnects in electronic packaging due to their relatively high melting point, attractive mechanical properties, thermal cycling reliability, and environment friendly chemical properties. The mechanical behavior of lead free solders is highly dependent on the operating temperature. Previous investigations on mechanical characterization of lead free solders have mainly emphasized stress-strain and creep testing at temperatures up to 125 °C. However, electronic devices, sometimes, experience harsh environment applications including well drilling, geothermal energy, automotive power electronics, and aerospace engines where solders are exposed to very high temperatures from 125–200 °C. Mechanical properties of lead free solders at elevated temperatures are limited. In this work, we have investigated the mechanical behavior SAC305 (96.5Sn-3.0Ag-0.5Cu) and SAC_Q (SAC+Bi) lead free solders at extreme high temperatures up to 200 °C. Stress-strain tests were performed on reflowed uniaxial specimens at four elevated temperatures (T = 125, 150, 175, and 200 °C). In addition, changes of the mechanical behavior of these alloys due to isothermal aging at T = 125 °C have been studied. Extreme care has been taken during specimen preparation so that the fabricated solder uniaxial test specimens accurately reflect the solder material microstructures present in actual lead free solder joints. High temperature tensile properties of the solders including initial modulus, yield stress, and ultimate tensile strength have been compared. As expected, our results show substantial degradations of the mechanical properties of lead-free solders at higher temperatures. With prior aging, these degradations become even more significant. Comparison of the results has shown that the addition of Bi to traditional SAC alloys improves their high temperature properties and significantly reduces their aging induced degradations.

Wire bonding is popular first-level interconnect method used in the semiconductor device packaging. Gold (Ag) wire is often used in high-reliability applications. Typical wire diameters vary between 0.8mil to 2mil. Recent increases in the gold-price have motivated the industry to search for alternate materials candidates for use in wirebonding. Three of the leading candidates are Silver (Ag), Copper (Cu), and Palladium Coated Copper (PCC). The new material candidates are inexpensive in comparison with gold and may have better electrical, and thermal properties, which is advantageous for fine pitch-high density electronics. The transition, however, comes along with few trade-offs such as narrow process window, higher wire-hardness, increased propensity for chip-cratering, lack of reliability knowledge base of when deployed in harsh environment applications. Relationship between mechanical degradation of the wirebond and the change in electric response needs to be established for better understanding of the failure modes and their respective mechanisms. Understanding the physics of damage progression may provide insights into the process parameters for manufacture of more robust interconnects. In this paper, a detailed study of the electrical and mechanical degradation of wirebonds under high temperature exposure is presented. Four wirebond candidates (Au, Ag, Cu and PCC) bonded onto Aluminum (Al) pad were subjected to high temperature storage life until failure to study the degradation of the bond-wire interface. Same package architecture and electronic molding compound (EMC) were used for all four candidates. Detailed analysis of intermetallic (IMC) phase evolution is presented along with quantification of the phases and their evolution over time. Ball shear strength was measured after decapsulation. Measurements of shear strength, shear failure modes, and IMC composition have been correlated with the change in the electrical response. Change in shear strength and different shear failure modes for different wirebond systems are discussed in the paper.

A DfR (Design for Reliability) approach which is systematically based on simulation, sensitivity analysis and experimental validation is applied for identifying, understanding and controlling the key factors which determine the solder joint reliability of eWLB (Embedded Wafer Level Ball Grid Array) packages that carry embedded 77 GHz dies and sit on hybrid PCB (Printed Circuit Board) stacks. The hybrid stack investigated in this work is characteristic to automotive RADAR (Radio Detection And Ranging) applications and consists of one low-loss RF (Radio Frequency) layer and several FR4 layers. In line with previous work [1], the mechanical material properties of the low-loss RF laminate material are found to be the key factor. Simulation is used to systematically screen for mechanical properties which are favorable for achieving a high solder joint reliability on the unconstrained PCBs used for standardized solder joint reliability testing. A simplified virtual assessment of PCBs constrained by the mounting in system module housings is done. Both simulation and experimental results show that RF laminate materials with low Young’s modulus are the class of materials which allows for the highest solder joint reliability for all the conditions investigated in this study.

The increasing complexity of electronics in systems used in safety critical applications, such as for example self-driving vehicles requires new methods to assure the hardware reliability of the electronic assemblies. Prognostics and Health Management (PHM) that uses a combination of data-driven and Physics-of-Failure models is a promising approach to avoid unexpected failures in the field. However, to enable PHM based partly on Physics-of-Failure models, sensor data that measures the relevant environment loads to which the electronics is subjected during its mission life are required. In this work, the feasibility to manufacture and use integrated sensors in the inner layers of a printed circuit board (PCB) as mission load indicators measuring impacts and vibrations has been investigated. A four-layered PCB was designed in which piezoelectric sensors based on polyvinylidenefluoride-co-trifluoroethylene (PVDF-TrFE) were printed on one of the laminate layers before the lamination process. Manufacturing of the PCB was followed by the assembly of components consisting of BGAs and QFN packages in a standard production reflow soldering process. Tests to ensure that the functionality of the sensor material was unaffected by the soldering process were performed. Results showed a yield of approximately 30% of the sensors after the reflow soldering process. The yield was also dependent on sensor placement and possibly shape. Optimization of the sensor design and placement is expected to bring the yield to 50 % or better. The sensors responded as expected to impact tests. Delamination areas were present in the test PCBs, which requires further investigation. The delamination does not seem to be due to the presence of embedded sensors alone but rather the result of a combination of several factors. The conclusion of this work is that it is feasible to embed piezoelectric sensors in the layers of a PCB.

The coarse heterogeneous microstructure of SAC alloys makes the behavior of interconnections highly sensitive to its geometric length-scale. Heterogeneous integration and the resulting increase in package complexity and miniaturization are making this scale-effect ever more important. This scale effect derives from the anisotropy of tin and the coarse multi-tiered microstructural heterogeneities in SAC solders. As a result, no two joints behave the same and every joint is unique depending on its specific microstructure. Product teams responsible for reliable heterogeneous integration have to ensure that they have adequate methods to deal with this variability. This paper highlights the multi-tiered microstructural morphology in SAC solders due to the solidification and crystallization process. At the highest tier in the joint microstructure are individual (highly anisotropic) grains that can be 100s of microns in size. At the next lower tier the primary heterogeneity is due to individual dendrites of pro-eutectic β tin, that can have lobes as large as 10–20 microns. At the next lower tier the characteristic heterogeneity is a eutectic mix of nanoscale Ag 3 Sn IMC particles dispersed in a Sn matrix. Researchers have long recognized that the grain morphology is extremely important to mechanical behavior of BGA solder joints because they are coarse-grained (i.e. there may be only a few anisotropic grains in each BGA solder joint). However, heterogeneous integration has now led to joints that are much smaller (less than 100 microns tall), thus making them of the same length-scale as individual tin dendrites within each grain. In other words, there may be just a few dendrites through the thickness of the joint. Unfortunately, very little attention has focused on SAC behavior at such a small length-scale. This study focuses on the effect of the tin-dendrite morphology on the effective behavior of SAC solder joints, using a combination of experiments and multi-tiered anisotropic models that combine dislocation nano-mechanics with composite micromechanics. The volume fraction of β-Sn dendrite within one crystal could vary from 20% to 80%, depending on the time and temperature above the liquidus temperature and the cooling rates. The effects of volume fraction and aspect ratio of Sn dendrites on the anisotropic steady-state creep rate of single crystal SAC specimen are examined. The objective of the study is to provide insights into the role that solder microstructural heterogeneity will play on package reliability in heterogeneous integration.

AlGaN/GaN high electron mobility transistors (HEMTs) are widely used in high frequency and power applications of the space and military industries due to their high RF power densities. When operated in full capacity, reliability of GaN HEMTs drop significantly due to device degradation, electron collapse phenomena, and concentrated heating effects. Although significant research has been done to investigate the effects of passivation, field-plates on the device degradation and the electron collapse separately, combined electrothermal analysis of the field-plates and the SiO 2 passivation on GaN HEMTs has not been performed from the perspective of device reliability. For this purpose, electrothermal simulations of the field-plated and non-field-plated devices with different SiO 2 passivation thicknesses are performed using Sentaurus TCAD to obtain the electrical field distribution and Joule heating caused temperature distribution in operating devices. Using these results, electrical and thermal effects of the field-plates on the devices with different SiO 2 passivation thicknesses are analyzed to obtain the most effective and reliable operating conditions.