This paper describes a method for the synthesis of silica nanoparticles that can be later used for coating of quantum dots inside a microfluidic reactor. Here, a droplet-based system is used where two reagents were mixed inside the droplets to obtain silica. Particles in the size range of 25±2.7 nm were obtained with comparable size distribution to controlled batch-wise synthesis methods. This method is suitable to be used later to coat CdSe nanoparticles inside the microreactor.

The information technology (IT) industry is exploring three-dimensional (3D) stacking of chips to maintain future computing scalability. However, 3D chip stacks require a solution to significant new thermal challenges. Interlayer two-phase evaporative cooling with a chip-to-chip interconnect-compatible dielectric fluid is an enabling technology but faces significant development issues. One such issue is the inability to thermally model a microprocessor with spatially varying heat sources together with a two phase microfluidic convection network. While progress has been made on two-phase conjugate simulations at the chip and channel levels, none of those provide a computationally manageable approach. In the present study, a reduced physics conjugate heat transfer model has been developed for simulating two-phase flow boiling through chip embedded micron scale cavities. This model has been validated with good accuracy against data available from literature. The validated model was then extended to predict the thermal performance of a state-of-the-art microprocessor chip with embedded two-phase cooling, where significant improvements in device junction temperatures were observed compared to the baseline cooling solution.

This paper reports on a proof-of-concept study of applying a two-dimensional (2D) microfluidic-based tactile sensor for tissue palpation under the influence of misalignment. Two unavoidable misalignment issues, uncertainty in contact point and non-ideal normal contact, severely distort the genuine elasticity distribution of a tissue region, yielding false identification of abnormality. The core of the 2D tactile sensor is one whole microstructure embedded with an electrolyte-enabled 2D resistive transducer array underneath. This unique configuration allows the tactile sensor to interact with a tissue region in a continuous manner that mimics manual palpation: the whole microstructure (fingertip) presses a tissue region and the corresponding deflection distribution is captured concurrently by the embedded transducer array (distributed sensors under the skin). This continuous manner tackles the misalignment issues encountered by an individual sensor or a sensor array, in that any misalignment encountered by the 2D sensor is manifested as an increasing trend of the distributed deflection-depth relations along the tilt direction. Tissue phantoms with embedded nodules and extrusions are prepared and are measured using the 2D tactile sensor, validating the capability of the tactile sensor to identify abnormalities in soft tissue under the influence of misalignment.

We report on experimental demonstration of multilayer molybdenum disulfide (MoS 2 ) nanomechanical resonators integrated on microchannels, with the potential for resonant operation and sensing applications in microfluidics. Microchannels with width of ∼5μm and depth of ∼1–2μm are fabricated on polydimethylsiloxane (PDMS) substrate. We transfer MoS 2 flakes with both singly-clamped cantilever and doubly-clamped membrane structure onto the PDMS channels, and measure both undriven thermomechanical resonances and optically driven responses from the devices. The devices show up to 6 thermomechanical resonances, with highest resonance frequency ( f res ) of 16.3MHz and quality ( Q ) factor ∼200. This type of MoS 2 nanomechanical resonators, when integrated with microfluidics in microchannels, would make new interesting candidates for biosensing and chemical sensing in fluids.

This paper reports on a microfluidic-based tactile sensor capable of detecting forces along two directions and torque about one direction. The 3-Degree-Of-Freedom (3-DOF) force/torque sensor encompasses a symmetric three-dimensional (3D) microstructure embedded with two sets of electrolyte-enabled distributed resistive transducers underneath. The 3D microstructure is built into a rectangular block with a loading-bump on its top and two microchannels at its bottom. Together with electrode pairs distributed along the microchannel length, electrolyte in each microchannel functions as a set of three resistive transducers. While a normal force results in a resistance increase in the two sets of transducers, a shear force causes opposite resistance changes in the two sets of transducers. Conversely, a torque leads to the opposite resistance changes in the two side transducers in each set. Soft lithography and CNC molding are combined to fabricate a prototype tactile sensor. The experimental results validate the feasibility of using this microfluidic-based tactile sensor for 3-DOF force/torque detection.

GaN on Diamond has been demonstrated to enable notable increases in RF power density without impacting High Electron Mobility Transistor (HEMT) peak junction temperature. However, Monolithic Microwave Integrated Circuits (MMICs) fabricated using GaN on Diamond substrates are subject to the same packaging thermal limitations as their GaN on SiC counterparts. Therefore, efforts to exploit GaN on Diamond to achieve substantial increases in MMIC power are stymied by external packaging thermal resistances that characterize the current “remote cooling” paradigm. This paper explores an intra-chip cooling alternative to the “remote cooling” paradigm, eliminating various heat spreader, heat sink and thermal interface layers in favor of integral microfluidic cooling in close proximity to the device junction. We describe an intra-chip cooling structure comprised of GaN on Diamond with integral micro-channels fed using a Si fluid distribution manifold. This structure exploits GaN on Diamond substrate technology to support increased HEMT areal power density while employing diamond microfluidics to affect scalable, low thermal resistance die-level heat removal. Thermal-electrical-mechanical co-design of integrated circuit (IC) features is performed to optimize conjugate heat transfer performance and manage the electrical and mechanical impacts associated with the presence of fluidic cooling near the electrically active region of the device. Through this, MMICs with significantly greater RF output than typical of the current state-of-the-art (SoA), dissipating die and HEMT heat fluxes in excess of 1 kW/cm 2 and 30 kW/cm 2 , respectively, can be operated with junction temperatures that support reliable operation. The modeling, simulation and micro-fabrication results presented here demonstrate the potential of diamond microfluidics-based intra-chip cooling as a means to alleviate thermal impediments to exploitation of the full electromagnetic potential of GaN.

Embedded cooling techniques, utilizing microfluidic channels directly within a die substrate or in a miniature heat sink attached to the base of the die, have been known for decades [1] [2] [3]. Despite their demonstrated thermal benefits, such techniques and devices have not been successfully transitioned from the laboratory to either the commercial or military arena. Some of the hurdles preventing implementation to date have been the inability to miniaturize the supporting hardware, the high unit cost of fabricating individual microfluidic coolers, and the unknown reliability of the new technologies introduced. Recent advances in micro manufacturing and co-design/simulation capabilities have enabled significant progress to be made, aided by a significant new focus on embedded cooling technologies was recently initiated by DARPA [4]. This paper will present a recently fabricated embedded cooling system consisting of a state of the art, micro-miniature, 3D microfluidic manifold suitable for near term integration into existing systems. Computational fluid dynamics (CFD) and conjugate heat transfer (CHT) simulations demonstrate the ground breaking thermal performance achieved by the device, and coupled-field flow, thermal, structural and erosion simulations are also presented to address some of the reliability concerns. Finally, measured thermal performance is presented, validating the predicted thermal performance.

High aspect ratio microchannels using high thermal conductivity materials such as silicon carbide (SiC) have recently been explored to locally cool micro-scale power electronics that are prone to on-chip hot spot generation. Analytical and finite element modeling shows that SiC-based microchannels used for localized cooling should have high aspect ratio features (above 8:1) to obtain heat transfer coefficients (300 to 600 kW/m 2 ·K) required to obtain gallium nitride (GaN) device channel temperatures below 100°C. This work presents experimental results of microfabricating high aspect ratio microchannels in a 4H-SiC substrate using inductively coupled plasma (ICP) etching. Depths of 90 μm and 80 μm were achieved with a 5:1 and 12:1 aspect ratio, respectively. This microfabrication process will enable the integration of microchannels (backside features) with high-power density devices such as GaN-on-SiC based electronics, as well as other SiC-based microfluidic applications.

In this paper, a novel thermal testbed with an embedded micropin-fin heat sink is designed and fabricated. The micropin-fin array has a nominal height of 200 μm and a diameter of 90 μm. Single phase and two phase thermal testing of the micropin-fin array heat sink are performed using deionized (D.I.) water as the coolant below atmospheric pressure. The measured pressure drop is as high as 100 kPa with a mass flux of 1637 kg/m 2 s at a heat flux of 400 W/cm 2 in a two-phase regime. The heat transfer coefficient and the vapor quality are calculated and reported. The impact of microfluidic cooling on the electrical performance of the 3D interconnects is also analyzed. The high aspect ratio through silicon vias (TSVs) used in the electrical analysis have a nominal diameter of 10 μm.

Three-dimensional integration (3D IC) is a new technology that shows great potential for high performance and energy efficiency. However past work has shown that 3D ICs suffer from serious thermal issues, and advanced cooling solutions such as micro-fluidic cooling are necessary to realize the true potential of these systems. The interactions between thermal, electrical and physical aspects of a 3D design with micro-fluidic cooling are substantial, and a comprehensive co-design approach to address them simultaneously is a must. Such co-design techniques are required throughout the design process, including during architectural design space exploration (DSE) in order to ensure that optimal design choices are not overlooked. In this paper we propose a DSE framework for 3D CPUs with micro-fluidic cooling that applies electro-thermal optimization techniques to the circuit layout and the heatsink design. By considering such physical optimization techniques we provide a more accurate view of a 3D architecture’s thermal and timing feasibility, as well as its performance and energy efficiency. Using our proposed thermo-electrical-physical co-design DSE framework we are able to improve performance by 1.54x and energy efficiency by 1.26x.

Three-dimensional (3D) chip stacking is a promising approach for high performance microsystems. Such vertical integration could increase the clock frequency and reduce the signal delay. During operation, the input signal and the resulting input power change with time. Realistic power maps on active chip tiers produce highly non-uniform heat flux patterns with hotspots, which change with time. In this paper, a transient compact model of a multi-layer chip stack subjected to time dependent power map was developed. Inter-tier single phase microfluidic cooling with a pin fin array was used to enhance heat transfer. The validity of the compact model was confirmed by comparison with full computational fluid dynamics/heat transfer (CFD/HT) modeling. It was found that the transient compact model ran thousand times faster than the CFD/HT model. The maximum deviation between the two models was 1 °C. The compact model was then used to analyze the transient thermal response of a 4 layer dual core stack of Penryn microprocessors when a total power of 172.4 W with a 300 W/cm 2 hot spot was suddenly applied. The hotspot temperature rise approaches 35 °C, at a steady state time of about 0.015 s. The temperature rise of bottom tier was always higher than the other three tiers during the transient process because it has only single side cooling, while other tiers have double sided cooling. Also, different power maps and flow patterns, including parallel and counter flow for different layers were investigated. It was found that controlling the flow in different layers individually instead of applying the same flow conditions could achieve better thermal performance and energy savings.

Two-phase microfluidic heat sinks promise high heat flux cooling at reduced pumping power compared to pumped liquid microchannel heat sinks. However, flow instabilities caused by bubble nucleation and expansion severely reduce heat transfer performance of two-phase microfluidic heat sinks. This study probes the governing physics of bubble nucleation and expansion by comparing the effects of pulsed heating to steady-state heating in a single microchannel. Pulsed heating at 8 Hz causes an increase in the average hotspot temperature of as much as 8°C compared to steady-state heating. Upstream and downstream temperature response does not vary significantly between heating conditions. The results correspond well with thin-film evaporation models for bubble growth. This study provides insight for designing two-phase microfluidic cooling system subjected to transient hotspots.

Two-phase microfluidic cooling solutions have the potential to meet the thermal and geometric requirements of high performance microprocessors. However, rapid nucleation and growth of the vapor phase in the micro-scale flow structures produce detrimental rise in the system pressure and create flow instabilities. In our previous work we developed a novel solution to these problems: to locally vent the vapor formed in the microstructures by capping the flow structures with porous, hydrophobic membranes that allow only the trapped vapor phase to escape the system. In this paper we present the results from a visualization study of this venting process in a copper microchannel with a porous hydrophobic Teflon membrane wall and determine the impact of varying flow conditions on the venting process. We tested liquid flow rates of 0.1, 0.25 and 0.5 ml/min with air injection rates varying from 0.2 to 6 ml/min, corresponding to mass qualities of 0.1% to 7%. Bubbly/slug and wavy flows are dominant at the lower liquid and air flow rates, with wavy-stratified and stratified flows becoming dominant at higher air injection rates. At the highest liquid flow rate, plug and annular flows were common. Analysis finds that venting effectiveness is insensitive to Re liq until the point where non-contact flow structures such as annular become dominant and result in a loss of effective venting area. We also find that venting area changes linearly with mass quality and that the maximum venting effectiveness can be improved by increasing the venting area or raising the total static system pressure. However, venting effectiveness is fundamentally limited by the membrane conductance.

This paper describes microscale fluidic chip I/O interconnects to enable the delivery of a coolant from substrate-level fluidic channels to a CMOS chip with an integrated silicon microchannel heat sink. It is shown that the fluidic I/Os are flip-chip compatible and can be assembled simultaneously with C4 bumps. The cooling of >300 W/cm 2 is demonstrated using the microfluidic chip I/Os. Their compatibility with optical I/Os and the mechanical compliance characterization of the optical I/Os are also described. Experimental research is reported in the fabrication, assembly, and testing of a chip with electrical and fluidic I/O interconnects.

Heat sinks for next generation microprocessors must remove increasing levels of power with non-uniform spatial distribution (hotspots). Two-phase convection promises strongly reduced pump size but is challenging because of boiling flow instabilities. This work studies parallel microchannel boiling stability using a series of dual channel devices which are fabricated with varying lateral thermal resistance and integrated heaters and thermometers. The data are consistent with a demand curve analysis predicting flow distribution and wall temperatures in thermally isolated parallel channels with strictly fluidic interaction. Increasing the thermal resistance between two parallel channels is shown to strongly influence the onset of instabilities and adversely increase the peak temperature. These dual-channel experiments capture the key physics of multichannel instabilities and provide the foundation for improved design of two-phase microfluidic heat sinks.

In molding, geometric variation of molded parts is inevitable since the parts have a thermal history, including expansion and shrinkage, during the molding process. Shrinkage induces variation between the designed dimensions and locations of features on molded parts while the parts are cooled. Characterization of the variation is necessary to ensure dimensional and location integrity. Hot embossing and injection molding were performed in order to assess variation. Measurements were made using a Measurescope (MM-22, Nikon Corp., Kawasaki, Japan). The measured locations and dimensions were compared to estimates obtained using a simple model based on the linear thermal expansion coefficients (CTE) of the molded materials. The measured and the estimated shrinkage from hot embossing were incorporated in the fabrication of microtiter plate-based polymer microfluidic platforms.

We demonstrate a prototype chip-scale microfluidic cooling scheme. CMOS compatible processes allow the monolithic integration of the microchannel heat sink into the backside of a Si chip at low temperature (≤260°C). At the front side of a chip, fine pitch area-array solder bumps are fabricated by electroplating for high-density electrical I/O interconnection, while a peripheral array of micro polymer pipes are fabricated as thermal-fluidic I/O interconnects. The resulting “microfluidic flip chip” can be bonded onto a liquid-cooled board substrate using conventional flip-chip assembly processes. The cooling liquid can, therefore, be transferred into a Si chip directly from the board-level manifolds to alleviate the thermal interface issues. This paper was also originally published as part of the Proceedings of the ASME 2005 Heat Transfer Summer Conference .

The paper describes the configuration effects of the auxiliary parts on the flow behavior around the microfluidic device. Recent development of the devices in MEMS is noticeable. The devices are manufactured in more complicated configuration and arrangement with the auxiliary part for the requirement of higher performance. An evaluation of the flow field around the microfluidic device is strongly required in MEMS design. The aim of the paper is to clarify the effect of the auxiliary part arrangement on the flow field around the micro flow sensor which has both the sensing element and the auxiliary parts such as the pins, pillars and electric bonding wires. The flow around the sensor is measured by using the Micro Particle Image Velocimetry (PIV) system. We investigate four types of the micro flow sensor with different configuration and arrangement of the pin, the bonding wires and the pillars. The result shows that the effect of the supporting pillars is negligible.

A variety of fabrication techniques have been used to make microfluidic microsystems: bulk etching in silicon and glass, plastic molding and machining, and PDMS (silicone) casting. Surprisingly the most widely used method of integrated circuit (IC) fabrication (surface micromachining — SMM) has not been extensively utilized in microfluidics despite its wide use in MEMS. There are economic reasons that SMM is not often used in microfluidics; high infrastructure and start-up costs and relatively long fabrication times: and there are technical reasons; packaging difficulties, dominance of surface forces, and fluid volume scaling issues. However, there are also important technical and economic advantages for SMM microfluidics relating to large-scale batch, no-assembly fabrication, and intimate integration of mechanical, electrical, microfluidic, and nano-scale sub-systems on one chip. In our work at Sandia National Laboratories MDL (Microelectronics Development Lab) we have built on the existing MEMS SMM infrastructure to produce a variety of microfluidic microsystems. These example microsystems illustrate the challenges and opportunities associated with SMM microfluidics. In this paper we briefly discuss two SMM microfluidic microsystems (made in the SUMMiT™ and SwIFT™ processes — www.mdl.sandia.gov/micromachine ) in terms of technical challenges and unique SMM microfluidics opportunities. The two example microsystems are a DEP (dielectrophoretic) trap, and a drop ejector patterning system.

In this study, a hybridized neural-genetic optimization methodology realized by embedding finite element analysis (FEA) trained artificial neural networks (ANN) into genetic algorithms (GA) is used to optimize temperature control in a ceramic based continuous flow polymerase chain reaction (CPCR) device. The CPCR device requires three thermally isolated zones of 94°C, 65°C and 72°C for the corresponding process of denaturing, annealing and extension to complete a cycle of polymerase chain reaction. Three separately addressable heaters provide heat input to each zone, microfluidic channels allow for the transport of fluid between zones and thermal isolation between the zones is maintained by machining air-gaps into the device. The most important aspect of temperature control in the CPCR is to maintain temperature distribution at each reaction zone with a precision of ±1°C or better irrespective of changing ambient conditions. Results obtained from the FEA simulation are compared with published experimental work. Simulation results show good comparison with experimental work for the temperature control in each reaction zone of the microfluidic channels. The data is then used to train the ANN to predict the temperature distribution of the microfluidic channel for new heater input power and fluid flow rate. Using these data, optimization of temperature control in the CPCR device is achieved by embedding the trained ANN results as a fitness function into GA. The objective of the optimization is to minimize the temperature difference in each reaction zone of the microfluidic channel while satisfying the residence time requirement. Finally, the optimized results for the CPCR device are used to build a new FEA model for numerical simulation analysis. The simulation results for the neural-genetic optimized CPCR model and the initial CPCR model are then compared. The neural-genetic optimized model shows a significant improvement from the initial model establishing the optimization methods superiority.