Applications of printed sensors have increased to industrial, consumer electronics, and medical fields with the advancements in the technology of printing and the adaptability of ink. These sensors are used to monitor a variety of measurements, including temperature, humidity, strain, and sweat, with different systems. This paper studies the performance characteristics of additively printed strain sensors using a nScrypt machine with a direct-write printing technique. The ink used in this study is silver ink which is thermally cured and also has a solderable property. The thermal curing temperature and trace width of the printed silver trace is optimized for better performance in the strain measurements, shear load to failure, and resistivity. Once the printing characteristics of the trace are defined, strain gauges are printed on printed wiring boards (PWB) and are tested at different loading and temperature environments. The sustainability and repeatability of the sensor measurements at high-stress conditions are studied using combined temperature and vibration loads of up to 50 degrees Celsius and 10g acceleration levels. The strain characteristics of the printed strain gauges are studied by comparing them to a commercial strain gauge at a similar position on the test substrate. The repeatability and variation of the strain profile are studied with different conditions of temperature and acceleration conditions at different time instants during vibration. The gauge factor of the printed strain gauge is quantified using a 3-point bending experiment with printed and commercial strain gauges at symmetrical locations of the substrate.

Printed electronics has found new applications in wearable electronics owing to the opportunities for integration, and the ability of sustaining folding, flexing and twisting. Continuous monitoring necessitates the production of sensors, which include temperature, humidity, sweat, and strain sensors. In this paper, a process study was performed on the FR4 board while taking into account multiple printing parameters for the direct-write system. The process parameters include ink pressure, print speed, and stand-off height, as well as their effect on the trace profile and print consistency using white light interferometry analysis. The printed traces have also been studied for different sintering conditions while keeping the FR4 board’s temperature limit in mind. The paper also discusses the effect of sintering conditions on mechanical and electrical properties, specifically shear load to failure and resistivity. The data from this was then used to print strain gauges and compared them to commercially available strain gauges. By reporting the gauge factor, the printed strain gauge has been standardized. The conductive ink’s strain sensing capabilities will be studied under tensile cyclic loading (3-point bending) at various strain rates and maximum strains. Long-term performance testing will be carried out using cyclic tensile loads.

Graphene has great potential for ultra-sensitive strain sensors applications due to its high mechanical strength and good compatibility with the traditional semiconductor process. In the current study, we investigated the effect of tensile and bending deformations on the electronic states of graphene nanoribbons (GNRs) using density functional theory (DFT) to clarify the underlying mechanism of the piezoresistive properties of graphene. It is found that the electronic structure of armchair graphene nanoribbons (AGNRs) is very sensitive to the tensile deformation. When a uniaxial tensile stress is applied to AGNRs with width N a = 10, the band structure is modified, leading to the change in band gap approximately from 0 eV to 1.0 eV. The band gap values of bent AGNRs decrease significantly when the maximum local dihedral angle exceeds a critical value due to the orbital hybridization. Based on these knowledge, we fabricated a strain sensor using the graphene film grown by thermal chemical vapor deposition (CVD) method on Cu foil. The strain sensor is fabricated directly on the graphene-coated Cu foils by using the standard photolithography process and reactive ion etching (RIE) and then transferred onto a stretchable and flexible polydimethysiloxane (PDMS) substrate. The one-dimensional tensile test and three-dimensional bending test are performed to investigate the piezoresistive properties. A gauge factor 3.4 was achieved under the tensile deformation. The fabricated strain sensor also exhibits good performance to detect bending deformation.

Stress sensing test chips are a powerful tool for measuring in-situ stresses in electronic packages. In this study, we have applied (111) silicon test chips to perform a variety of measurements of die stresses in plastic packages. In particular, stresses were characterized in 240 pin Quad Flat Packs (QFPs) subjected to various thermal and moisture loadings. The utilized 10 × 10 mm sensor chips incorporated optimized eight-element piezoresistive rosettes that were capable of measuring the complete state of stress at the die surface (including the interfacial shear stresses). The fabricated test chips were initially used to measure die stresses in the QFPs after molding and post mold bake. Measurement results were correlated with finite element simulations of the molding process. Subsequently, the effects of thermal cycling on the measured die stress distributions for selected packages were investigated. After these initial measurements, the samples were stored at room temperature and ambient humidity for 17 years. The samples were then re-measured after this long term storage to evaluate the degree of die stress relaxation that had occurred. Several packages were then exposed to a harsh high temperature and high humidity environment (85 C, 85% RH) for various time durations, and allowed to absorb moisture. The die stresses at several locations were characterized as a function of time during the hygrothermal exposure. The weight variations in each sample were also measured during the 85/85 exposure to gauge the moisture uptake, and reversibility tests were conducted to see whether the effects of moisture uptake were permanent. Using these measurements and numerical simulations, valuable insight has been gained on moisture induced failure phenomena in plastic packages. Good agreement was found between the predicted and measured die normal stress distributions occurring after molding of the QFP. The magnitudes of the in-plane normal and shear stresses were found to have decreased by up to 30% after moderate levels of thermal cycling. After long term storage, the experimental measurements showed that the die normal stresses in the QFPs relaxed significantly (up to 40%), while the die shear stresses exhibited only small variations. In addition, the 85/85 hygrothermal exposures had strong effects, generating tensile die normal stress changes of up to 130 MPa. Upon fully redrying in reversibility tests, it was observed that the moisture-induced normal stress changes were not recovered. Good correlations were observed between the variations of sample weight (increases in moisture content) and the variations of the die normal and shear stress changes.

Free-standing electrically conductive nanotube and nano-bridge structures offer a simple, small-scale, low-power option for pressure and temperature sensing. To sense pressure, a constant voltage is applied across the bridge. At small scales, the heat transfer coefficient is pressure-dependent. The change in the heat transfer coefficients result in the circuit operating at higher temperatures, with different resistances, at low pressures. This in turn will lead to a change in the electrical resistivity of the system. If the system is held at constant voltage, this can be measured as a change in the current in such systems, representing a simple alternative to existing Pirani gauges. The current work simulates the Joule heating, conduction and convection heat transfer of a 5 micron long suspended single-wall carbon nanotube, incorporating temperature-sensitive material properties. The simulation allows prediction of the thermo-electrical response of the systems. The results agree with the trends observed in existing devices. Additional results look at the effects of system length, temperature, and contact resistances between the substrate and the device.

A new highly sensitive strain measurement method has been developed by applying the strain-induced change of the electronic conductivity of CNTs. It is reported that most multi-walled carbon nanotubes (MWCNTs) show metallic conductivity and they are rather cheap comparing with single-walled carbon nanotubes (SWCNTs). However, it was found that the electric conductivity of MWCNTs changes drastically under uniaxial strain because of the drastic change of their band gap. Therefore, the authors have developed a highly sensitive strain sensor which can detect the local strain distribution by using MWCNTs. In order to design a new sensor using MWCNT, it is very important to control the shape of the MWCNTs under strain. Thus, a method for controlling the shape of the MWCNTs was developed by applying a chemical vapor deposition (CVD) technique. It was found that the shape of the grown MWCNT could be controlled by changing the average thickness of the catalyst and the deposition temperature of the MWCNT. The electrical resistance of the grown MWCNT changed almost linearly with the applied strain, and the maximum strain sensitivity obtained under the application of uniaxial strain was about 10%/1000-μstrain (gauge factor: 100). A two-dimensional strain sensor, which consists of area-arrayed fine bundles of MWCNTs, has been developed by applying MEMS technology. Under the application of compressive strain, the electric resistance was confirmed to increase almost linearly with the applied strain.

Constrained by low thermodynamic efficiencies, thermoelectric generators (TEGs) require a comparatively large amount of heat to produce a given quantity of electricity. Therefore, further improvements in thermoelectric designs are needed. In this paper, a coupled-field thermoelectric model, which presents a rigorous interfacial energy balance by capturing Joule heating, Seebeck, Peltier and Thomson effects, is developed to gauge the feasibility of the two promising solutions to enhance power generated by the TEGs, utilizing the commercial FEA package COMSOL™ through the Physics Interface Builder. First, the patterned topography on wall surfaces is implemented and the improved performance has been observed by introducing stirred flows into the heat exchangers and equalizing the temperature across the channels. Referring to the analysis, approximately 10% enhancement in power generation can be addressed for the base-relief TEG. Second, the prospect of increasing the thermal transport capability of water by loading CuO nanoparticles in the TEGs with multi-scale heat exchangers is explored. It is found that the conversion performance of the water/CuO nanofluid-based TEG is superior when compared to the water-based TEG at the micro-scale, where the flow rate is relatively low. The significant insight is gained to fabricate the ideal TEGs with optimum power performance.

R thJA (Junction-to-Ambient Thermal Resistance) for power device packages was measured and modeled in order to correlate the results from our experiments and simulations. The packages studied, including TO (Transistor Outline), DFN (Dual Flat Non-Leaded), SOP (Small Outline Package) and DPAK with sizes from 3×3mm to 15×10mm, were tested under natural convection environment. An important observation from our testing is the significant influence of the external wires connecting the test coupon to the power supply on the thermal resistance value derived from the test data. The increase in the R thJA based on the test is more than 50% for TO packages and 19% for smaller packages once the external wires changed from gauge 18 to 30. A simple yet effective simulation approach was then introduced to predict R thJA incorporating the critical influence from the external wire size variation. With the validated finite element model, the effects of package factors such as package outline, die size, die attach, encapsulation and interconnection on the thermal resistances of the power semiconductor packages were studied by simulation to provide further insights and guides for new package developments.

Since the thickness of the stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the thermal residual stress distribution appears in the stacked chips due to the periodic alignment of metallic bumps, and they deteriorate the reliability of products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are discussed quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of 4 gauges with different crystallographic directions. This alignment of strain gauges enables to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made by silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper layer was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the rigid joint formation by alloying with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed experimentally that both the hound’s-tooth alignment between a TSV (Through Silicon Via) and a bump and control of mechanical properties of electroplated copper thin films used for the TSV and bump is indispensable in order to minimize the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process induced stress in 3D stacked chips quantitatively.

As the legislatures demand the use of lead (Pb) free plating finishes in lead frame manufacturing, different plating finishes are being offered by the lead frame makers. Lead frames are most often designed with two different Pb free plating finishes, primarily tin and nickel/palladium (Ni/Pd) based. The tin post mold plated lead frames use silver selective plating on the lead fingers for secondary wire bonding whereas the pre-plated Ni/Pd based lead frames use the same Ni/Pd based finish throughout. Enhanced versions of Ni/Pd based plating finishes such as nickel/palladium/gold (Ni/Pd/Au), nickel/palladium/gold-palladium (Ni/Pd/Au-Pd) and nickel/palladium/gold-silver (Ni/Pd/Au – Ag) are now available to further improve the wirebondability, solderability and reliability of the package. The development of a new lead frame finish involves a wide variety of concerns which must be addressed and thus mandates further evaluation of these new structures. Using the common Pb free lead frame plating finish of selectively plated silver (Ag) as the basis, a comparative approach was used to evaluate the secondary wire bond integrity of a 25 micron (1 mil) thick gold wire on Ni/Pd based lead frame plating finishes. The integrity of the secondary wire bonds for different plating finishes was investigated at various assembly thermal exposure stages using the wire pull strength test as the arbiter. Reliability tests, such as High Temperature Storage (HTS) and Unbiased Highly Accelerated Stress Test (UBHAST), were also conducted. Finally, failure analysis was conducted with the help of metallographic cross sectioning, SEM/EDX (Scanning Electron Microscope/Energy Dispersive X-ray) analysis and statistical analysis of the wire pull strength test results. Before wire bonding the lead frames, the plating surface was investigated for its surface integrity with the help of plating quality tests, such as: (i) adhesive tape test, (ii) bend test, (iii) heating test and the (iv) scribing test. Also, since wire pull is a destructive test, a statistical method called a nested gauge R&R study was used to estimate the repeatability and reproducibility of the measurement system. Failure analysis showed that there were silver and copper migrations over the Ag plated lead frame when exposed to a high temperature storage test at 175°C for 1000 hrs, but this did not affect the bond integrity. However, the Ni/Pd based lead frames did not show any metal migration since nickel acts as a barrier against the base metal diffusion.

As the microelectronics industry continues to trend towards smaller, lighter, and higher power devices, thermal management is becoming more important than ever. Thermal interface materials (TIMs) play a crucial role in removing heat from both bare die and lidded packages. A serious challenge the industry has been facing is the lack of an agreed upon test standard that is specifically tailored for TIM thermal performance measurements between TIM suppliers and OEM customers. ASTM D 5470 is not necessarily the best gauge for TIMs in-application performance. Data generated by the OEM often differ from TIM supplier’s results, and thus can not be used confidently in thermal design. An OEM’s material selection can also prove to be unreliable when comparing data from different TIM suppliers. This paper presents a successful model that an OEM customer (Sun Microsystems) and a TIM supplier (LORD Corporation) have established for characterization of TIMs, and illustrates a package-level thermal test vehicle (TTV) setup for junction-to-sink thermal resistance measurements. Also presented are test results for several TIMs and repeatability of the test method. The effects of a few influencing factors, such as pressure load and TIM staging time, on the test results are also discussed.

The major focus of this work was the determination of the nine constants required for Anand’s viscoplastic constitutive model for a lead-free solder alloy, 95.5Sn3.8Ag0.7Cu and to compare them with those for SnPb. The test specimen was a cast dog bone shape based on ASTM E 8M-01, with a diameter of 4mm and a gauge length of 20mm. A series of tensile experiments were carried out: constant displacement tests ranging from 6.5 × 10 −5 /s to 1.0 × 10 −3 /s at temperatures of 20°C, 75°C, and 125°C; constant load tests at a range of loads from 10MPa to 65MPa, also at temperatures of 20°C, 75°C, and 125°C. A series of non-linear fitting processes was used to determine the model constants. Comparisons were then made with experimental measurements of the stress-plastic strain curves from constant displacement rate tests: it was found that the model matched the experimental data at low strain rates but did not capture the strain hardening effect, especially at high strain rates. A finite element model of the test was also constructed using ANSYS software. This software includes the Anand model as an option for its range of viscoplastic elements, requiring that the nine constants be input. In this case, an 8-noded axisymmetric element (VISCO108) was used to model the test specimen under constant displacement rate loading. The model was then used to predict the stress-plastic strain curve and this was compared to both the experimental measurements and the fitted Anand model. Reasonable agreement was found between the Anand model and the FE predictions at small strain rates. Finally, a BGA device was simulated under accelerated temperature cycling conditions using ANSYS with the fitted Anand for the SnAgCu solder joints. A Morrow-type fatigue life model was applied using empirical constants from two published sources and good agreement was found between experiment and predicted fatigue life.

The high residual stress in an electronic package sometimes causes not only mechanical failure but also the instability of electronic functions. Therefore the residual stress in resin-molded electronic packages should be evaluated. In this paper, the residual stress in a resin-molded electronic package was evaluated by the combination of experimental method using a test chip including piezoresistive gauges and the finite element method (FEM). The linear thermal elastic analysis of the resin-molded electronic package was carried out using the three dimensional FEM model. Stress-free temperature for the analysis was experimentally determined using the piezoresistive test chip. It was demonstrated that the residual stress at room temperature obtained by the FEM analysis well corresponds with the stress measured using the test chip. It was found from the results that compressive residual stress of over 100MPa was distributed on the top surface of a semiconductor chip in a plastic package. This study presents a simple evaluation technology of the residual stress in resin-molded semiconductor chips using the combination of experimental and numerical methods.

Local residual stress at a surface of a silicon chip mounted on a substrate using flip chip technology was measured using a stress sensor chip that was composed of 168 strain gauges of 10-μm in length. Each strain gauge was made of polycrystalline silicon films deposited on a silicon wafer. The periodic stress distribution was measured at a surface of the sensor chip between two bumps. Five gauges were aligned at a interval of 20-μm between the bumps. When the thickness of the chip was less than 200 μm, the amplitude of the stress increased drastically, as was predicted by a finite element analysis. The amplitude of the stress reached about 150 MPa, when the thickness of the chip was thinned to 50 μm. The amplitude of the stress is a strong function of the thickness of a silicon chip and the intervals of the bumps.