SnBi based solder alloys become an interesting alternative for standard SnAgCu as they can be used to solder components at much lower temperature. The typically 50°C lower solder reflow temperature is less damaging for PCB and components, and also prevents hot tear and head-in-pillow failures for large fine pitch BGA components. A reasonable concern for these low-melting temperature solders is the thermal cycling reliability performance, in particular for harsh conditions such as automotive products. In this work, thermal cycling testing and failure analysis have been performed on 9 × 9 mm size QFN components and large chip components (2010 and 2512) which are typically sensitive to thermal fatigue. The results are benchmarked to standard SAC alloy. Also the process advantages from the low temperature solder alloys are depicted in this paper. Finally, the effect of Pb contamination on this SnBi based solder is investigated.

Facebook Datacenter consists of a large number of servers that run diverse Facebook services aggregated to serve any given user request. To allow this aggregation, servers have to interact with each other via different traffic flows which are managed by networking fabric. The underlying connection powering this fabric consists of a large number of pluggable optical interconnects and On Board Optical (OBO) modules carrying production data. This connectivity at scale requires fast and reliable detection of the link failures to ensure resolution. In the first generation of the deployments, detection of the link failure was sequential and a slow process. The troubleshoot process was equally tedious as the available tools required characterizing one optical transceiver at a time. Further, the failure analysis also presented a majority of resolution with no failed optics as a root cause resulting in high No Trouble Found (NTF) rate. In this paper we introduce a novel link failure detection and resolution method that improves on the previous method across three dimensions: faster resolution, reliable troubleshooting and scalable implementation. We introduce BER Illusion Methodology (BIM) that is a highly scalable and resource efficient solution that significantly reduces the time taken to troubleshoot pluggable optical interconnects. This is also scalable to next-gen OBO modules at Facebook datacenters aiming to lower the NTF rate and optimally utilizing the available resources. BIM, which is based on Open Compute Platform (OCP) network switches, can be used to troubleshoot 128 QSFP28, 64 QSFP56 or 32 OBO modules simultaneously in under 30 minutes. The tool is easy to implement and capable of also reporting diagnostics on the transceiver such as Transmitter Power, Transmitter Bias Current, Receiver Power, Case Temperature, Bit Error Rate result per channel, Vendor information and Manufacturing part number. This additional test data report along with true failure indication helps optic suppliers gain confidence and build customer credibility. The open-source nature and the universal applicability of this tool offers possibility for other users to adopt and further customize it for their networking needs.

Accelerated life testing (ALT) has been a common choice to study the effects of environmental stresses on flexible hybrid electronics (FHE), a promising technology to produce flexible electronic devices. Nevertheless, accelerated degradation testing (ADT) has proven to be a more effective approach, which does not require failure occurrences, allowing shorter testing times. Since FHE devices are expected to be highly reliable, ADT provides useful information in the form of degradation data for further analysis without actual failure data. In this paper, we present the design and experimental setup of ADT for FHE considering two stress factors simultaneously. We use daisy-chain resistance as a measurable degradation characteristic to periodically monitor the degradation of FHE products under accelerated stress conditions. Two stress factors, temperature and humidity, are considered and ADT was carried out considering four combinations of temperature and humidity simultaneously. Failure analysis was performed on failed units to investigate the failure process and location of the failure. The ADT data was used to fit in the appropriate mathematical degradation model representing the failure process. The data analysis showed faster degradation paths for higher stress combinations. Finally, we present insights and further research opportunities to expand the work.

There is a growing need for flexible hybrid electronics solutions for wearable applications, in which the user may often wear electronics on body, on fabric or on skin. Electronics in wearable application may be subjected to stresses of daily motion including bending, twisting and stretching. Thus, there is need for technologies capable of flexibility, robustness and small size while being lightweight. Existing standards for focus on rigid electronics and there is scarcity of guidance for test-levels needed to assure reliability of flexible electronics. There is need for studies focused on the development of accelerated test conditions representative of field applications and the identification of failure mechanisms for test levels. In this study, experimental analysis on fatigue life of the PCB in cyclical folding load is conducted. A folding test-stand capable of replicating the stresses of daily motion in a lab-environment has been developed for the test. For the better understanding of the failure mechanism, analysis of failure modes is carried out. Consequently, it is found that fatigue life of the PCB is related to the several conditions: folding direction, moving distance, folding diameter and strain rate.

As the automotive industry shifts towards the electrification of drive trains, the efficiency of power electronics becomes more important. The use of silicon carbide (SiC) devices in power electronics has shown several benefits in efficiency, blocking voltage and high temperature operation. In addition, the ability of SiC to operate at higher frequencies due to lower switching losses can result in reduced weight and volume of the system, which also are important factors in vehicles. However, the reliability of packaged SiC devices is not yet fully assessed. Previous work has predicted that the different material properties of SiC compared to Si could have a large influence on the failure mechanisms and reliability. For example, the much higher elastic modulus of SiC compared to Si could increase strain on neighboring materials during power cycling. In this work, the failure mechanisms of packaged Si- and SiC-based power devices have been investigated following power cycling tests. The packaged devices were actively cycled in 4.5 s heating and 20 s cooling at ΔT = 60–80 K. A failure analysis using micro-focus X-ray and scanning acoustic microscopy (SAM) was carried out in order to determine the most important failure mechanisms. The results of the analysis indicate that the dominant failure mechanism is wire bond lift-off at the device chip for all of the SiC-based devices. Further analysis is required to determine the exact failure mechanisms of the analyzed Si-based devices. In addition, the SiC-based devices failed before the Si-based devices, which could be a result of the different properties of the SiC material.

This work experimentally studies the impact of facility cooling failure of a direct liquid cooling (DLC) system on the IT equipment (ITE). The facility side of a DLC system removes the heat from a secondary loop — in direct contact with the ITE — and discard it in a chiller loop or ambient. The CPU utilization and coolant set point temperature (SPT) are varied to understand the effect of failure under different operating conditions. The ITE response is studied in terms of chip temperature and power, and fan speed. It was found that failure of the facility cooling system is not hazardous to the IT operation. The rate of change in temperature after failure is low and is sufficient to turn the ITE off safely. This is attributed to the surrounding air in the data center and the thermal mass of the cooling system.

In this paper, the impact of direct liquid cooling (DLC) system failure on the IT equipment is studied experimentally. The main factors that are anticipated to affect the IT equipment response during failure are the CPU utilization, coolant set point temperature (SPT) and the server type. These factors are varied experimentally and the IT equipment response is studied in terms of chip temperature and power, CPU utilization and total server power. It was found that failure of the cooling system is hazardous and can lead to data center shutdown in less than a minute. Additionally, the CPU frequency throttling mechanism was found to be vital to understand the change in chip temperature, power, and utilization. Other mechanisms associated with high temperatures were also observed such as the leakage power and the fans speed change. Finally, possible remedies are proposed to reduce the probability and the consequences of the cooling system failure.

Modern day data centers are operated at high power for increased power density, maintenance, and cooling which covers almost 2 percent (70 billion kilowatt-hours) of the total energy consumption in the US. IT components and cooling system occupy the major portion of this energy consumption. Although data centers are designed to perform efficiently, cooling the high-density components is still a challenge. So, alternative methods to improve the cooling efficiency has become the drive to reduce the cooling cost. As liquid cooling is more efficient for high specific heat capacity, density, and thermal conductivity, hybrid cooling can offer the advantage of liquid cooling of high heat generating components in the traditional air-cooled servers. In this experiment, a 1U server is equipped with cold plate to cool the CPUs while the rest of the components are cooled by fans. In this study, predictive fan and pump failure analysis are performed which also helps to explore the options for redundancy and to reduce the cooling cost by improving cooling efficiency. Redundancy requires the knowledge of planned and unplanned system failures. As the main heat generating components are cooled by liquid, warm water cooling can be employed to observe the effects of raised inlet conditions in a hybrid cooled server with failure scenarios. The ASHRAE guidance class W4 for liquid cooling is chosen for our experiment to operate in a range from 25°C – 45°C. The experiments are conducted separately for the pump and fan failure scenarios. Computational load of idle, 10%, 30%, 50%, 70% and 98% are applied while powering only one pump and the miniature dry cooler fans are controlled externally to maintain constant inlet temperature of the coolant. As the rest of components such as DIMMs & PCH are cooled by air, maximum utilization for memory is applied while reducing the number fans in each case for fan failure scenario. The components temperatures and power consumption are recorded in each case for performance analysis.

MEMS microphones are extensively used in many applications that require reliability, small size, and high sound quality. For harsh environment reliability data MEMS microphones need to be monitored under conditions mimicking their areas of applications. MEMS microphones have an opening/sound port in order to interact with the environment, therefore cannot be sealed completely since the sensing mechanism requires interaction between sound waves and the sensing element. Little to no information exists on reliability data for MEMS microphones under low/high temperature operating life and temperature humidity bias condition. Our work is primarily focused on providing harsh environmental reliability data which can be useful to MEMS designers and engineers. In this paper the test vehicles with MEMS Microphones have been tested under three different harsh environmental conditions: high temperature operating life (HTOL) at 125°C at 3.3V, low temperature storage (LTS) at −35°C and temperature humidity 85°C/85%RH at 3.3V. The main motive of this study is to document the incremental shift and degradation in output parameters namely distortion, frequency response, power supply rejection capability of IC, frequency vs pressure characteristics and analog output voltage of the MEMS microphone. The survivability of MEMS microphone, ADMP401, has been demonstrated as a function of change in the output parameters. Failure analysis has been conducted on the microphone samples to study failure modes and sites using analytical methods such as SEM, EDS and X-ray.

Fracture mechanics is an essential field of study towards the improvement and development of electronic packages. In combination with modern simulation method such as finite element analysis (FEA), fracture mechanics is widely used and appreciated in the industry. Many different approaches have been developed to calculate the fracture parameters for interfaces or bulk material under given loads in order to compare them against previously measured failure criteria. While many publications are available that have described the different simulation approaches in detail or compare the different fracture test methods, there have been few comparisons of these simulation approaches with respect to their use in research and development of electronic packages. The objective of this work is to compare different delamination modeling methodologies and their applications for electronic packaging. The work highlights the differences in theory behind each approach as well as the differences in their practical use to predict delamination or asses a fracture risk in electronic packages. The intention was to use commercially available FE-codes in conjunction with a well-defined set of adhesion strength tests. During this work, energy based fracture criteria were applied by means of the virtual crack closure technique (VCCT), the J-integral and the cohesive zone material model (CZM) methods. These methodologies are most commonly used but can differ significantly from each other as will be shown in this comparison. To demonstrate the use of these techniques, copper lead frame to epoxy mold compound (EMC) delamination was assessed, representing a very common packaging failure mode. Critical energy release rates were measured on multiple Copper-EMC test specimens under varying load phase angles. ANSYS was used to build mechanical simulation models of a selected device. Existing post processing procedures were applied to assess delamination risk based on above mentioned techniques. The simulation study considers realistic monotonic loading conditions and results will also be compared to existing failure analysis images for demonstration and validation purpose. As an outcome, the paper will include a ranking of the approaches as well as a summary of advantages and disadvantages, based method and accuracy. An outlook on future developments such as fatigue or aging phenomena will finish the work.

Decapsulation is one of the very powerful technique in failure analysis process. During this process, die and first level interconnects are exposed by dissolving molding compound around them using variety of methods. Typically decapsulation formulation uses red fuming nitric acid at elevated temperatures. This technique work for traditional Gold wire bonds, but does not work for its new alternative Copper. Gold, being inert metal does not react with acid. Copper on the other hand; tends to react with fuming nitric acid, and dissolves rapidly into acid. It is important to develop acid chemistry that can be successfully used to perform decapsulation of Cu-Al incorporated packages for different EMC’s. In this paper, decap process based on combination of red fuming nitric acid and concentrated sulfuric acid at elevated temperatures is presented. Reduction in wire diameter was monitored for all devices. For some devices decap process was evaluated based on comparison of WB shear strength of decaped part with unmolded part. SEM was used extensively to track down degradation of copper wires. These tests were performed on packages with different EMC’s, wire diameters, pad thickness and some active dies. Statistical principal components regression model has been developed correlating the decapsulation process parameters with the post decap wire diameter reduction. Principal component regression in conjunction with stepwise regression has been used to identify the influential variables, and to remove the multicollinearity between the predictor variables. Principal component analysis which combines two correlated variables into a single factor is a widely used image processing technique for pattern recognition and image compression. The post molded packages have then used to assess the effect of various decapsulation treatments.

Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG), which has been used in component packaging, has been gaining attention as a surface finish for printed wiring boards. The primary role of a printed wiring board surface finish is to provide a solderable surface for assembly, creating a reliable solder interconnect. With regards to reliability, the increased use of mobile electronics has resulted in the need to consider the ability of interconnects to withstand repeated mechanical shocks. This paper examines the drop reliability of both SnPb and SAC305 interconnects formed on ENEPIG finished printed wiring boards. For comparison, the drop reliability test results for similar boards with Immersion Silver (ImAg) board finish are included. Test boards include BGA and resistor packages. The boards are dropped 500 times to achieve failure across the components. Failure analysis revealed that the dominant failure mode for BGA packages on the ENEPIG finish was cracking in the solder balls at the component interface, while for the ImAg finish the dominant failure mode was cratering in the board laminate below the solder pad. For the resistor packages, cracking through the solder joint at the component interface was the dominant failure mode for both the ENEPIG and ImAg finishes. The drop results indicate that both finishes are suitable for systems that could experience mechanical shock due to drop, with components soldered onto ENEPIG with a SAC 305 solder having the highest survivability. The combination of SnPb and ImAg was found to be superior to SAC 305 and ImAg.

Thermal characterization is useful for identifying the cause of circuit failures. Unusually high local temperatures can occur due to unexpected and localized power dissipation in a particular device, which was not anticipated nor designed in the device. Unintended high temperatures may be the source of circuit damage or it might be caused by the failure itself, such as a tiny short-circuit. However, it is often difficult to obtain enough information about the physical structure and characteristics of the circuit to clearly identify the cause of the failure. The method we present here is an imaging technique with both thermal distribution and emission intensity superimposed on a single image. Thermoreflectance thermal imaging takes advantage of the differences in light reflectivity of the surface with a changing temperature. This relationship is quite linear in a typical temperature range of interest. Using 1300 nm wave length for the illuminating source, the metal circuitry of interest is directly observed through the almost transparent silicon substrate of a flip chip mounted device. With the same photo detecting imaging sensor, i.e. InGaAs junction array, the emission from the target device through the silicon substrate is also detected. If there are some local electron collisions, e.g. due to a current concentration at a defect or a tiny whisker, a localized excess energy by electron-electron collision yields the photon generation and emits an electromagnetic wave. The photons having a sufficient energy level at wavelength transparent to silicon, reach the photo detecting imaging sensor. With software processing and precise synchronization of the driving circuit, illumination, and imaging, we can separate the thermal signal from the emission and observe transient behavior on a nanosecond time scale. The time response is helpful in some cases to separate cause and effect. As an example, an unintended small short-circuit resulting from the fabrication process may be reproduced for a small number of samples. The emission would be observed first, followed by the thermal signal which propagates in time. Another example is for a circuit with low design margin, in this case only a single sample exhibits a difference between emission and/or thermal image while numbers of good samples are identical with respect to the emission and thermal image. This difference clearly indicates the location of a potential failure.

Pastes consisting of micron-sized particles of a low melting point metal (i.e. Sn) and a high melting point metal (e.g. Ag, Cu) embedded in organic binder have been developed to attach silicon or wideband gap semiconductor devices to metallic or ceramic substrates for power electronic applications requiring operation at high temperatures. The attachment is made by a pressure-less, low temperature transient liquid phase sintering (LT-TLPS) process in air. Process time and temperature, along with binder type and amount are adjusted to minimize the formation of voids in the joints. Test samples consisting of copper dice on copper substrates joined by these LT-TLPS sinter pastes have been manufactured for shear testing. A shear fixture for high-temperature testing has been designed, and shear tests have been performed at temperatures of 25°C, 125°C, 250°C, 400°C, and 600°C. The influence of process time, process temperature, and the ratio of low-melting point metal (Sn) to high-melting point metal (Ag, Cu) on the shear strength at each temperature has been assessed. It has been shown that the shear strength of TLPS sinter joints remains high up to the melting point of the dominant intermetallic phase of the joint. The joints show no softening below the melting point of these phases. AgSn sinter joints show only limited change in shear strength up to 400°C. CuSn joints exhibit high shear strength up to 600°C for high copper ratios. While process times of 5–15 minutes are sufficient to drive the sintering reaction to near completion, extended curing improves the strength of the sinter joints even more. Failure analyses for joints of different compositions have been conducted along with cross-sectioning of sintered but non-sheared specimens to correlate reliability to microstructure.

The effect of Cu-filled through-silicon vias (TSVs) interposers on the reliability of 3D IC integration system-in-package (SiP) is investigated in this study. Emphasis is placed on the determination of the stresses at the Cu-low-k pads on a Moore’s law chip and the creep strain energy density per cycle at the corner solder joints between the Moore’s law chip and an interposer. Also, thermal cycling tests and failure analysis results of a test vehicle is presented and discussed.

The ever increasing power density in modern semiconductor devices requires heat dissipation solution such as heat sink to remove the heat away from the device. A compressive loading was applied to reduce the interfacial thermal resistance between package and heat sink. In this study both numerical modeling and experimental approaches were employed to study the effect of compressive loading on the interconnect reliability, especially for high power density package, under thermal cycling loading conditions. The JEDEC standard thermal cycle tests were conducted and the resistance of the daisy chained circuits was in-situ measured to record the failure time. The failure analysis has been performed to indentify the failure modes of solder joint with and without the presence of compressive loading. A finite element based thermal fatigue life prediction model for SAC305 solder joint under compressive loading was also developed and validated with the experimental results.

Extensive failure analysis was performed on identical, isothermally cycled wafer-level chip scale packages with Sn3.8wt%0.7wt%Ag (SAC387) solder joints. Packages were periodically removed during the cycling process to observe crack front progression. The packages were dipped in liquid nitrogen to reduce solder ductility and then pried apart. The crack areas were observed under an optical microscope. The average crack areas on the corner and mid-edge joints of the package were measured using an image processing software. 50 packages were characterized from 240 to 7200 cycles at every 240 cycles. An average of 20 solder joints per cycle was observed to estimate the crack length and area. A finite element model of this package was constructed in ABAQUS. The solder interconnects of the model were given full plastic and creep properties. Using the failure analysis data and the finite element model, the material constant value in a previously developed hierarchal fracture model was calibrated for SAC387. The ability of the model to predict non-intuitive failure initiation sites due to the under bump metallurgy (UBM) geometry is demonstrated. The hierarchal fracture process model was inspired by information theory and continuum thermodynamics. It was earlier proposed to capture the length-scale and temporal hierarchy inherent in quasi-static fracture processes. This single parameter model allows for a non-empirical, geometry independent approach to predicting crack growth by relating equivalent inelastic dissipations and a material constant to the probability of fracture at a material point.

As the legislatures demand the use of lead (Pb) free plating finishes in lead frame manufacturing, different plating finishes are being offered by the lead frame makers. Lead frames are most often designed with two different Pb free plating finishes, primarily tin and nickel/palladium (Ni/Pd) based. The tin post mold plated lead frames use silver selective plating on the lead fingers for secondary wire bonding whereas the pre-plated Ni/Pd based lead frames use the same Ni/Pd based finish throughout. Enhanced versions of Ni/Pd based plating finishes such as nickel/palladium/gold (Ni/Pd/Au), nickel/palladium/gold-palladium (Ni/Pd/Au-Pd) and nickel/palladium/gold-silver (Ni/Pd/Au – Ag) are now available to further improve the wirebondability, solderability and reliability of the package. The development of a new lead frame finish involves a wide variety of concerns which must be addressed and thus mandates further evaluation of these new structures. Using the common Pb free lead frame plating finish of selectively plated silver (Ag) as the basis, a comparative approach was used to evaluate the secondary wire bond integrity of a 25 micron (1 mil) thick gold wire on Ni/Pd based lead frame plating finishes. The integrity of the secondary wire bonds for different plating finishes was investigated at various assembly thermal exposure stages using the wire pull strength test as the arbiter. Reliability tests, such as High Temperature Storage (HTS) and Unbiased Highly Accelerated Stress Test (UBHAST), were also conducted. Finally, failure analysis was conducted with the help of metallographic cross sectioning, SEM/EDX (Scanning Electron Microscope/Energy Dispersive X-ray) analysis and statistical analysis of the wire pull strength test results. Before wire bonding the lead frames, the plating surface was investigated for its surface integrity with the help of plating quality tests, such as: (i) adhesive tape test, (ii) bend test, (iii) heating test and the (iv) scribing test. Also, since wire pull is a destructive test, a statistical method called a nested gauge R&R study was used to estimate the repeatability and reproducibility of the measurement system. Failure analysis showed that there were silver and copper migrations over the Ag plated lead frame when exposed to a high temperature storage test at 175°C for 1000 hrs, but this did not affect the bond integrity. However, the Ni/Pd based lead frames did not show any metal migration since nickel acts as a barrier against the base metal diffusion.

Quad Flat No lead (QFN) packages are being used as alternative components to some of the large form-factor packages due to their smaller footprint, improved thermal and electrical performance. During the past few years, there has been a surge of published papers by end users and component manufacturers on the topic of assembly and reliability of the QFN packages. Both empirical and simulation data has been published, which has helped several manufacturers to develop design guidelines and assembly processes for these packages. There exists a gap in the current published work on the assembly and reliability of high I/O count QFNs on thick boards. In addition, reliability of the rework process on QFNs is not well documented. Therefore, objectives of this research were the following: • Evaluate the second level reliability in thermal cycling for reworked and non-reworked QFNs; • Evaluate the reliability of different sized QFNs on 125 mil thick boards and compare with existing literature; • Failure analysis and recommendations for reliability improvement; • Land pattern comparison; and • Rework process improvement. Studies have been conducted on different QFN packages between 32 pins and 164 pins on 125 mil thick boards with Organic Solder Preservative (OSP) surface finish. Experimental design includes the use of different package sizes, alternate thermal pad patterns, and use of tin-lead versus lead free processes. A subset of some of the package types has also been reworked using variations of the standard BGA rework processes to evaluate its reliability. All packages were daisy chained. Boards were subjected to thermal cycling test between 0 to 100 deg C for 6000 hours. Data is analyzed using Weibull distribution. Failure mechanisms have been analyzed using dye penetration tests and cross sections. The reliability results are discussed in terms of package construction, type of land patterns and rework. Recommendations for process improvement are delineated.

Increasing power and I/O demands in HDI (high density interconnect) components coupled with the industry-wide conversion to lead-free products has introduced additional risk for solder joint reliability (SJR) of BGA (ball grid array) Flip-Chip electronic packages. One particular concern is SJR under mechanical shock (dynamic bend) loading. While leaded alloys provided good performance in shock for many years due to the unparalleled ability of lead’s slip systems to absorb the energy in shock events, lead-free alloys cannot provide the same benefit. To mitigate this risk, better approaches for understanding damage propagation are needed to enable better design to limit and reduce the SJR risk during shipping and end-user handling. To this end, a characterization study is undertaken to monitor damage progression at the second-level interconnect in BGA’s on flip-chip electronic packages during mechanical shock loading. The study uses a board-level, strain-monitoring approach plus the dye and peel failure analysis technique to track the initiation and propagation of solder joint cracks under loading. The approach being used differs from conventional reliability testing in that both design and load variables are used to quantify damage growth and strain response to bridge the understanding of design feature impact to traditional reliability testing. The scope of the study includes investigating the impact of such factors as package placement, board layout, and enabling load on the monitored board strain and the damage propagation observed. From this study, directions and design guidelines for improving solder joint reliability of future BGA’s on flip-chip electronic packages under mechanical shock loading conditions are proposed.