Abstract Significant advances are needed to optimize the charging speed, reliability, safety, and cost of today’s conservatively designed electric vehicle charging systems. The design and optimization of these novel engineering systems require concurrent consideration of thermal and electrical phenomena, as well as component- and system-level dynamics and control to guarantee reliable continuous operation, scalability, and minimum footprint. This work addresses the concurrent thermal and electrical design constraints in a high-density, on-board, bi-directional charger (referred to as power-hub) with vehicle-to-grid (V2G), grid-to-vehicle (G2V), vehicle-to-house (V2H) and vehicle-to-vehicle (V2V) power transfer capabilities. The electrical design of this charger consists of dc-dc and dc-ac power stages connected in series. The power-stage circuits are implemented on a Printed Circuit Board (PCB) with 16 surface-mount Silicon Carbide (SiC) MOSFETs, three inductors and one transformer. The main goal of this work is to investigate the interplay between the cooling architecture and the PCB layout, and the corresponding impact on the heat dissipation and parasitic inductance. This work compares the performance of three prototypes of this multifunctional charger using multi-physics simulations and experimental tests.

Abstract Flexible printed circuits (FPCs) are widely used in electronic devices such as movable part line or wearable sensor. Photolithography is one of the most popular processes for fabricating electric interconnect lines. However, inkjet printing has attracted attention because the method can draw an arbitrary-shape electric lines without any mask. Therefore, nanoparticle metal ink is widely used for printing of conductive electric lines with lowering cost and small-lot production. The physical characteristics such as flexibility or durability of metal nanoparticle ink lines have been evaluated by bending or tensile tests. By contrast, the evaluation method has not been sufficiently established for the electrical characteristics of these lines, and the failure mechanism under high-current density has not been clarified. According to scaling down of electric devices, current density and Joule heating in device lines increase and electromigration (EM) damage becomes a serious problem. EM is a transportation phenomenon of metallic atoms caused by electron wind under high-current density. Reducing EM damage is extremely important to enhance device reliability. In this study, current loading tests of metal nanoparticle ink line were performed to discuss damage mechanism and evaluate electrical reliability under high-current density condition. As the results of current loading tests, the thickness of cathode part of straight-test line was decreased. It is considered that atomic transport from the cathode to the anode occurred by EM phenomenon. The line surface became rough and aggregates of particles generated at middle or anode parts of straight-test line by high-current loading. Both of atomic transport and aggregate generation were closely related the changes of potential drop, their dominances were varied depending the current density value.

Abstract With the increase of electronic device power density, thermal management and reliability are becoming increasingly important. First, increased density challenges the capability of conventional heat sinks to adequately dissipate heat. Secondly, higher frequency switching in wide bandgap power modules is introducing new issues in electromagnetic interference (EMI) in which metallic heat removal systems will couple and create damaging current ringing. Lastly, lightweight heat removal is required to meet the increasing needs of mobile power systems. In this effort we introduce an additive manufacturing pathway to produce custom-tailored heat removal systems using non-metallic materials, which take advantage of convective heat transfer to enable efficient thermal management. Herein, we leverage the precision of AM techniques in the development of 3D optimized flow channels for achieving enhanced effective convective heat transfer coefficients. The experimental performance of convective heat removal due to liquid impingement is compared with conventional heat sinks, with the requirement of simulating the heat transfer needed by a high voltage inverter. The implementation of non-metallic materials manufacturing is aimed to reduce EMI in a low weight and reduced cost package, making it useful for mobile power electronics.

Abstract Electronic components in downhole oil drilling and gas industry applications, automotive and avionics may exposed to high temperatures (> 150°C) and high strain rates (1–100 per sec) during storage, operation and handling which can contribute to the failures of electronics devices. Temperatures in these applications can exceed 200°C, which is closed to melting point for SAC alloys. The microstructure for lead free solder alloys constantly evolves when subjected to thermal aging for sustained periods with accompanying degradation in mechanical properties of solder alloys. In this paper, evolution of microstructure and Anand parameters for unaged and aged SAC (SAC105 and SAC-Q) lead free solder alloys at high strain rates has been investigated induced due to thermal aging. The microstructure of the SAC solder is studied using scanning electron microscopy (SEM) for different strain rate and elevating temperature. The thermal aged leadfree SAC solder alloys specimen has been tested at high strain rates (10–75 per sec) at elevated temperatures of (25°C–200°C). The SAC leadfree solder samples were subjected to isothermal aging at 50°C up to 1-year before testing. To describe the material constitutive behavior, Anand Viscoplastic model has been used. Effect of thermal aging on Anand parameters has been investigated. In order to verify the accuracy of the model, the computed Anand parameters have been used to simulate the uniaxial tensile test. FEA based method has been used to simulate the drop events using Anand constitutive model. Hysteresis loop and Plastic work density has been computed from FEA.

Abstract Field Programmable Gate Arrays (FPGA) are integrated circuits (ICs) which can implement virtually any digital function and can be configured by a designer after manufacturing. This is beneficial when dedicated application-specific runs are not time or cost-effective; however, this flexibility comes at the cost of a substantially higher interconnect overhead. Three-dimensional (3D) integration can offer significant improvements in the FPGA architecture by stacking multiple device layers and interconnecting them in the third or vertical dimension, through a substrate, where path lengths are greatly reduced. This will allow for a higher density of devices and improvements in power consumption, signal integrity, and delay. Further, it facilities heterogeneous integration where additional functionalities can be incorporated into the same package as the FPGA, such as sensors, memories, and RF/analog or photonic chips, etc. Traditionally, devices have always been laid out in a planar format. 3D integration is an architecture wherein multiple layers of planar devices are stacked and interconnected using through silicon vias (TSVs) in the vertical direction. This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field programmable gate array (3D-AFPGA) design based on an extension of preexisting 2D-FPGA tile designs. Since thermal management of 3D-AFPGA is important, numerical simulations performed to predict the temperature distribution and avoid the maximum junction temperature. The numerical thermal modeling for predicting the equivalent thermal conductivity in every layer and three-dimensional temperature fields in the 3D-AFPGA are developed and discussed.

Abstract One of the leading contributors to assembly and reliability issues in electronic packaging arises from warpage and interfacial stresses stemming from coefficient of thermal expansion (CTE) mismatch of the interfacing components. Trends toward miniaturizing and increasing density of the electronic packages exacerbate the assembly problems, leading to issues such as die cracking and board level assembly yield loss. One potential solution may be found in the inclusion of auxetic structures, which demonstrate negative Poisson’s ratio through re-entrant geometries, which has been investigated for use in augmented structural mechanics for impact energy absorption. Because of the unique structural design, auxetics become thicker perpendicularly under an applied tensile load, unlike typical material loading responses. This interesting behavior has opportunity for integration into electronic packages for stress mitigation under thermal cycling since the structures can disrupt the typical expansion behavior. Here, auxetic trace geometries and structures were evaluated in various packaging implementations (die and substrate level) for warpage and stress reduction under thermal cycling conditions. By replacing standard Manhattan-style layouts and power and ground plane features with re-entrant trace geometries, reductions in thermomechanically induced interfacial stresses were observed, in addition to considering heat spreading properties within a package. Herein, deformation of silicon chip with addition of raised re-entrant Evans auxetics and raised ellipse shape auxetic traces as well as deformation of direct bonded copper (DBC) substrate with and without re-entrant auxetic patterned pads are estimated and compared using Finite Element Analysis (FEA) in ANSYS software. To demonstrate the benefits of passive auxetic traces, a planar transformer with re-entrant Evans auxetic patterns on PCB layers has been examined under full-load operating condition and compared with a traditionally patterned transformers. A better thermal distribution and lower maximum temperature in the device are achieved by including auxetic patterned features. FEA simulation results also show stress reduction in windings and lower deformation in PCB layers. Inclusion of auxetic structures in passive metal deposition layers which are not part of the circuit is shown to reduce maximum stress and warp deflection, as well as improve thermal gradient distribution and reduce overall temperature for 2D planar and 3D stacked packages. Consequently, use of auxetic features may extend package reliability significantly.

The study of solder joint reliability is one of the priority issues in electronic packaging. Solder alloys experience a highly nonlinear material behavior when subject to thermal cycling. It is a time consuming and difficult task to study the behavior of solder joints using experimental approaches. Finite element analysis provides a more efficient way to better understand the behavior of solder joints when accurate material models are available. With the developments of FEA algorithms and computer resources, the analysis approaches used for electronic packaging assemblies have evolved from 2-dimensional to 3-dimensional analyses, with far fewer assumptions needed in the fully 3D case. In this paper, we compare different FEA approaches covering various 2D and 3D modeling techniques to understand their advantages and drawbacks, especially as related to simulation accuracy and efficiency. Several models for a typical BGA assembly were prepared and analyzed including traditional mesh continuity models (2D slice model, 3D slice model, and 3D quarter model), as well as advanced models that employ Multi-Point Constraints (MPCs) and submodeling (global/local models). The Anand viscoplastic model was used for the solder joint material behavior in all of the FEA approaches. For the 3D mesh continuity models, an optimal analysis approach has been proposed to achieve the best balance between the accuracy of the simulation result and numerical efficiency of the simulation. Mesh transitions were used to maintain mesh continuity between regions of different mesh densities. A best choice of load step size was also found to reduce overall simulation time. For the analysis using MPCs to to bond different meshes, two improved modeling strategies have been proposed including a suggested ratio of contacting elements and the use of multiple-MPC contact pairs to reduce overall mesh density of the FE model. An improved simulation simulation strategy using submodeling has also been developed to obtain the best compromise in the global and local models between the mesh quality and load step size. An improved geometric simplification of the solder joint for use with energy based fatigue criteria was developed. Finally, comparisons and suggestions were made for the best analysis approach when using FEA techniques to predict the behavior of solder joints in PBGA packages.

Wire bonding is popular first-level interconnect method used in the semiconductor device packaging. Gold (Ag) wire is often used in high-reliability applications. Typical wire diameters vary between 0.8mil to 2mil. Recent increases in the gold-price have motivated the industry to search for alternate materials candidates for use in wirebonding. Three of the leading candidates are Silver (Ag), Copper (Cu), and Palladium Coated Copper (PCC). The new material candidates are inexpensive in comparison with gold and may have better electrical, and thermal properties, which is advantageous for fine pitch-high density electronics. The transition, however, comes along with few trade-offs such as narrow process window, higher wire-hardness, increased propensity for chip-cratering, lack of reliability knowledge base of when deployed in harsh environment applications. Relationship between mechanical degradation of the wirebond and the change in electric response needs to be established for better understanding of the failure modes and their respective mechanisms. Understanding the physics of damage progression may provide insights into the process parameters for manufacture of more robust interconnects. In this paper, a detailed study of the electrical and mechanical degradation of wirebonds under high temperature exposure is presented. Four wirebond candidates (Au, Ag, Cu and PCC) bonded onto Aluminum (Al) pad were subjected to high temperature storage life until failure to study the degradation of the bond-wire interface. Same package architecture and electronic molding compound (EMC) were used for all four candidates. Detailed analysis of intermetallic (IMC) phase evolution is presented along with quantification of the phases and their evolution over time. Ball shear strength was measured after decapsulation. Measurements of shear strength, shear failure modes, and IMC composition have been correlated with the change in the electrical response. Change in shear strength and different shear failure modes for different wirebond systems are discussed in the paper.

The percentage of the energy used by data centers for cooling their equipment has been on the rise. With that, there has been a necessity for exploring new and more efficient methods like airside economization, both from an engineering as well as business point of view, to contain this energy demand. Air cooling especially, free air cooling has always been the first choice for IT companies to cool their equipment. But, it has its downside as well. As per ASHRAE standard (2009b), the air which is entering the data center should be continuously filtered with MERV 11 or preferably MERV 13 filters and the air which is inside the data center should be clean as per ISO class 8. The objective of this study is to design a model data center and simulate the flow path with the help of 6sigma room analysis software. A high-density data center was modelled for both hot aisle and cold aisle containment configurations. The particles taken into consideration for modelling were spherical in shape and of diameters 0.05, 0.1 and 1 micron. The physical properties of the submicron particles have been assumed to be same as that of air. For heavier particles of 1 micron in size, the properties of dense carbon particle are chosen for simulating particulate contamination in a data center. The Computer Room Air Conditioning unit is modelled as the source for the particulate contaminants which represents contaminants entering along with free air through an air-side economizer. The data obtained from this analysis can be helpful in predicting which type of particles will be deposited at what location based on its distance from the source and weight of the particles. This can further help in reinforcing the regions with a potential to fail under particulate contamination.

Flip chip (FC) packaging techniques in modern power electronics have enabled increased power density in module performance, but mechanical stresses induced by thermal expansion during inherent operating conditions in the power devices and packages create a need for understanding thermomechanical fatigue mechanisms that lead to reliability concerns. Moreover, in actual use, these mechanical stresses impact the reliable lifetime alongside thermal factors (such as diffusion and microstructural transformation) and other process history effects. This amalgam of damage inducing phenomena make development of a concise association between damage, fatigue, and stress factors difficult to determine. For reliability demonstration under fatigue loading, accelerated life testing (ALT), such as Thermal Cycling (TC), are commonly used in industry; however, long duration and expensive equipment required for TC limit its utility, especially when considering the high cost of wide-bandgap devices and modules, and the limitation of high temperature (> 150°C) testing standards. As a result, alternative test methodologies are needed to provide faster, cheaper, and design integrable reliability determination. In this work, an accelerated test methodology is introduced and designed to simulate these mechanical stresses at isothermal conditions, which is demonstrated using test chips that are analogous to power devices. By stressing these devices in a controlled environment, mechanical stresses become de-coupled from the design and temperature, such that useful lifetimes can be predictable. Mechanical shear stress was cyclically applied directly to device-relevant, flip-chip solder interconnects while monitoring cycles-to-failure (CTF). Also, Finite Element Analysis (FEA) is used to extract various damage metrics of different solder materials (including PbSn37/63, SAC305 and Nano-silver) in both thermal operation and the introduced alternative mechanical testing conditions. In doing so, test protocol translations to common qualification tests (or use condition thermal profiles) can be determined and are validated using the mechanical shear stress testing method. Plastic work density and maximum shear were calculated in the critical solder interconnects for different isothermal mechanical testing temperatures (22°C, 75°C, 100°C and 125°C) and the results are compared with the simulation results of different TC test conditions. This reliability determination with failure parameter isolation allows for improved integration with FEA modeling for a priori reliability prediction during the design process.

The ability to create 3D ICs can significantly increase transistor packing density, reduce chip area and power dissipation leading to possibilities of large-scale on-chip integration of different systems. A promising process for this application is the microscale additive manufacturing (AM) of 3D interconnect structures and capability of writing 3D metal structures with feature sizes of approximately 1 μm on a variety of substrates. Current microscale AM techniques are limited in their capabilities to produce 3D conductive interconnect structures. This paper presents the design and development of a new micro AM technique — microscale selective laser sintering (μ-SLS) — which overcomes many of the limitations of other micro AM processes to achieve true micron sized, electrically conductive features on a variety of substrates. This paper will present preliminary results from set of sintering experiments on copper (Cu) nanoparticle (NP) ink using the continuous wave (CW) laser to be employed in the μ-SLS system which will be compared to Cu NP sintering results produced with other laser sources such as nanosecond (ns) & femtosecond (fs) lasers. This study is important to estimate the optimum working range of fluence/irradiance to be used in the μ-SLS setup depending upon the laser employed. In general, it provides an experimental estimate of the sintering fluence/irradiance range of Cu NPs depending upon the type of laser used and compares their sintering quality based on morphology of sintered spots.

In raised floor data centers, tiles with high open area ratio or complex understructure are used to fulfill the demand of today’s high-density computing. Using more open tiles reduces pressure drop across the raised floor with the potential advantages of increased airflow and lower noise. However, it introduces the disadvantage of increased non-uniformity of airflow distribution. In addition, there are various tile designs available on the market with different opening shapes or understructures. Furthermore, a physical separation of cold and hot aisles (containment) has been introduced to minimize the mixing of cold and hot air. In this study, three types of floor tiles with different open area, opening geometry, and understructure are considered. Experimentally validated detail models of tiles were implemented in CFD simulations to address the impact of tile design on the cooling of IT equipment in both open and enclosed aisle configurations. Also, impacts of under-cabinet leakage on the IT equipment inlet temperature in the provisioned and under-provisioned scenarios are studied. Finally, a predictive equation for the critical under-provisioning point that can lead to a no-flow condition in IT equipment with weaker airflow systems is presented.

During the last few decades, the microelectronics packaging industry has moved into the 2.5D to 3D space for increased density, functionality, and speed. Similar concepts and ideas for developing 2.5D to 3D power electronics packaging are desired to achieve even greater efficiency and power density over conventional power electronics packaging methods. Wide-band gap (WBG) semiconductors, such as SiC and GaN, have accelerated the ability to shrink the volumetric size and weight of these power conversion systems, and thus improve overall power density metrics, due to their inherent high frequency, high temperature, and high voltage capabilities. WBG power semiconductor devices, with these attributes, thus make themselves excellent candidates for more aggressive packaging, compared to Si-derived packaging, in order to not only take full advantage of the WBG device ratings, but also to achieve high power densities of the overall power conversion systems. Already different/multiple power semiconductor devices are being combined by processing them together on the same die to boost electrical performance and increase power density. It can be assumed that further levels of integration will be sought after for the next levels of packaging to enable similar gains, especially with the advent of double side solderable die. The 3D stacking of die, components, and substrates creates the question of how well will each of these perform in close proximity to each other. This work focuses on the numerical simulation and experimental measurements to predict the temperature distribution of power converters built in a stacked fashion. Thermal models of a stacked power electronic switching unit — a silicon controlled rectifier and anti-parallel diode — are modeled under the assumption of equally sized die. Temperature field maps are generated for 20W to 250W of power dissipations across the power semiconductor die. Thermal models are then compared with matching experimental setups to observe the effect of switching unit placement attached to a given substrate on the die junction temperatures for various scenarios of thermal crosstalk. Results from this work are expected to aid in the development 2.5D to 3D power electronic packaging by predicting thermal performance of stacked, ultra-dense, WBG device -based packages.

Metal lines used in integrated circuits (ICs) become narrow for raising the device performance. Due to scaling down of the ICs, current density and Joule heating are increased, which induces electromigration (EM) damage. EM is transportation phenomena of metallic atoms caused by electron wind under high current density. EM leads to hillock and void formation in the metal line, thus EM should be considered to evaluate the performances of the device safe. It is known that a value of threshold current density which is critical current density of the EM damage exists in via-connected and passivated lines. In this study, the effect of line geometry on the threshold current density is discussed in the case of taper-shaped line. The evaluation method of threshold current density is conducted based on numerical simulation technique with building-up processes of atomic density distribution in the metal line by using a governing parameter of EM damage. As the simulation results, threshold current density increased in the cases of shorter line length, lower temperature, and wider width in cathode side. Furthermore, a new parameter was proposed for simplified evaluation of the threshold current density in taper-shaped lines. The evaluation method is able to apply various line shapes and conditions and it is expected to use for confirmation of the reliability of the lines in circuit design processes.

The constant increase in data center computational and processing requirements has led to increases in the IT equipment power demand and cooling challenges of high-density (HD) data centers. As a solution to this, the hybrid and liquid systems are widely used as part of HD data centers thermal management solutions. This study presents an experimental based investigation and analysis of the transient thermal performance of a stand-alone server cabinet. The total heat load of the cabinet is controllable remotely and a rear door heat exchanger is attached with controllable water flow rate. The cooling performances of two different failure scenarios are investigated. One is in the water chiller and another is in the water pump for the Rear Door Heat eXchanger (RDHX). In addition, the study reports the impact of each scenario on the IT equipment thermal response and on the cabinet outlet temperature using a mobile temperature and velocity mesh (MTVM) experimental tool. Furthermore, this study also addresses and characterizes the heat exchanger cooling performance during both scenarios.

Reservoir structures are often constructed in the interconnection to prevent the electromigration damages. In this study, a numerical simulation technique for analyzing the atomic density distributions in the line under high current density was used to evaluate the effects of reservoir length and location on the threshold current density considering void and hillock generations. The threshold current density is determined when the local atomic density in the line reaches the upper critical value for hillock creation or the lower critical value for void generation. Atomic density distributions in the line were simulated when cathode and anode reservoir lengths were changed. The threshold current density considering void formation became higher with longer cathode reservoir and shorter anode reservoir. However, opposite results obtained in the case of hillock formation. It was found that there was an optimum value of reservoir length, corresponding to both critical values of hillock and void initiation.

Most of the electronic devices manufactured are used in daily life and with the miniaturization process of these devices, in the day to day life there is a risk of drop impact failure. It has been important to analyze and ensure the reliability of any electronic devices under every type of loading. Drop impact is not only loading that can affect reliability, but the simultaneous thermal load, moisture, convection is also acting. Smaller devices like cell phones, laptops, tablets are more prone to accidental impact loads which create board interconnects failure by frequent drop occurrence. Therefore, a multi-dimensional approach is taking place in research to study product reliability. In this paper, comprehensive study of drop and shock test is done on Quad Flat No-lead (QFN) package board of two different thickness. The computation setup is done with thermal analysis by providing power to die of the package which creates non-uniform temperature distribution during the drop testing analysis. This way drop test is coupled with a thermal load which is more realistic analysis. Our study depends on young’s modulus, density, CTE, thermal conductivity, specific heat and Poisson’s ratio of the material. Therefore, Experimental work includes material properties characterization of two boards to get temperature dependent Coefficient of thermal expansion, poison’s ratio and young’s modulus values using Thermal mechanical analyzer (TMA), the Dynamic mechanical analyzer (DMA) and Universal testing machine. Finite element analysis (FEA) method is used for computational analysis. Effect of impact loading for two boards has been done to investigate board and solder joint reliability due thickness and layer stack-ups in PCBs in environmental condition and at elevated temperature. For computational analysis, the assembly is subjected to the drop test per JEDEC standards. [12] The main purpose of this work is to study the impact of drop test with the powered package and how the reliability of any assembly changes with changing the stiffness of printed circuit board. The comparison of the boards has been made to understand the effect of PCB layer stack-ups, thickness, and temperature effect on the reliability of solder interconnects by considering the stress-strain generation that is induced in the PCBs during the drop test.

Modern day data centers are operated at high power for increased power density, maintenance, and cooling which covers almost 2 percent (70 billion kilowatt-hours) of the total energy consumption in the US. IT components and cooling system occupy the major portion of this energy consumption. Although data centers are designed to perform efficiently, cooling the high-density components is still a challenge. So, alternative methods to improve the cooling efficiency has become the drive to reduce the cooling cost. As liquid cooling is more efficient for high specific heat capacity, density, and thermal conductivity, hybrid cooling can offer the advantage of liquid cooling of high heat generating components in the traditional air-cooled servers. In this experiment, a 1U server is equipped with cold plate to cool the CPUs while the rest of the components are cooled by fans. In this study, predictive fan and pump failure analysis are performed which also helps to explore the options for redundancy and to reduce the cooling cost by improving cooling efficiency. Redundancy requires the knowledge of planned and unplanned system failures. As the main heat generating components are cooled by liquid, warm water cooling can be employed to observe the effects of raised inlet conditions in a hybrid cooled server with failure scenarios. The ASHRAE guidance class W4 for liquid cooling is chosen for our experiment to operate in a range from 25°C – 45°C. The experiments are conducted separately for the pump and fan failure scenarios. Computational load of idle, 10%, 30%, 50%, 70% and 98% are applied while powering only one pump and the miniature dry cooler fans are controlled externally to maintain constant inlet temperature of the coolant. As the rest of components such as DIMMs & PCH are cooled by air, maximum utilization for memory is applied while reducing the number fans in each case for fan failure scenario. The components temperatures and power consumption are recorded in each case for performance analysis.

Recently, due to the increasing heat density of printed circuit boards (PCBs), thermal fatigue damage in the joints has exerted a more significant influence on the reliability of electronic components. Accordingly, the development of a new nondestructive inspection technology is strongly desired by related industries. The authors have applied a synchrotron radiation X-ray micro-tomography system to the nondestructive observation of micro-cracks. However, the reconstruction of CT images is difficult for planar objects such as PCB substrates, due to insufficient X-ray transmission in the direction parallel to the substrates. In order to solve this problem, a synchrotron radiation laminography system was developed to relax size restrictions on the observation samples, and was applied to the three-dimensional nondestructive evaluation of several kinds of solder joints, which were loaded under accelerated thermal cyclic conditions via thermal shock tests. Moreover, the thermal fatigue crack propagation process that occurs under actual PCB energization loading conditions will differ from that under the usual acceleration test conditions. In this work, the possibility of in-situ monitoring of the thermal fatigue crack propagation process using the laminography system was investigated at die-attached joints subjected to cyclic energization loading, which is close to the actual usage conditions of PCBs. The optical system developed for use in the laminography system was constructed to provide a rotation stage with a tilt from the horizontally incident X-ray beam, and to obtain X-ray projection images via a beam monitor. In this manner, the X-ray beam is sufficiently transmitted through the planar specimen in all projections. The observed specimens included several die-attached joints, in which 3 mm square ceramic dies had been mounted on a 40 mm square FR-4 substrate using Sn-3.0wt%Ag-0.5wt%Cu solder. Consequently, the laminography system was successfully applied to the in-situ monitoring of thermal fatigue cracks that appeared in the solder layer under cyclic energization. This was possible because the laminography images obtained in the energization state have a quality that is equivalent to those obtained in a non-energized state, provided that the temperature distribution of the specimen is stable. In addition, the fatigue crack propagation process can be quantitatively evaluated by measuring the crack surface area and calculating the average crack propagation rate. However, in some cases, the appearance of thermal fatigue cracks was not observed in a solder layer that had been loaded by the accelerated thermal cycle test. This result strongly suggests that delamination occurred at the interface, which indicates that the corresponding fracture mode was significantly influenced by the type of thermal loading.

Nowadays, datacenters heat density dissipation follows an exponential increasing trend that is reaching the heat removal limits of the traditional air-cooling technology. Two-phase cooling implemented within a gravity-driven system represents a scalable and viable long-term solution for datacenter cooling in order to increase the heat density dissipation with larger energy efficiency and lower acoustic noise. The present article builds upon the 4-part set of papers presented at ITHERM 2016 for a 15-cm height thermosyphon to cool a contemporary datacenter cabinet, providing new test data over a wider range of heat fluxes and new validations of the thermal-hydrodynamics of our thermosyphon simulation code. The thermosyphon consists of a microchannel evaporator connected via a riser and a downcomer to a liquid-cooled condenser for the cooling of a pseudo-chip to emulate an actual server. Test results demonstrated good thermal performance coupled with uniform flow distribution for the new larger range of operating test conditions. At the maximum imposed heat load of 158 W (corresponding to a heat flux of 70 W cm −2 ) with a water inlet coolant at 20 °C, water mass flow rate of 12 kg h −1 and thermosyphon filling ratio of 78%, the pseudo mean chip temperature was found to be 58 °C and is well below the normal thermal limits in datacenter cooling. Finally, the in-house LTCM’s thermosyphon simulation code was validated against an expanded experimental database of about 262 data points, demonstrating very good agreement; in fact, the pseudo mean chip temperature was predicted with an error band of about 1 K.