Nowadays microelectronic packaging has become a billion dollar business. Due to the increased material and production costs per package, manufacturing yield loss in this state-of-art business is expected to be at a bare minimum which is tough to persevere in a high volume manufacturing environment. Additionally, high performance and varied power computing needs in the electronic business demands microprocessors with different form factors and complex package designs. One of the most common joint which is extensively used in such a complicated package is the polymer to metal bonding. In the latest technology products involving high package warpage, interfacial bonding has to be strong enough to withstand the dynamic warpage and high mechanical stresses associated with it and hence the reliability of polymer to metal adhesion is critical. In this paper, fundamental mechanisms related to adhesion phenomena of polymer-metal interface are proposed. Adhesive failure modes related to polymer-metal bonding and key variables influencing the bonding of silicone based polymer material to nickel electroplated on copper in an integrated circuit heat spreader assembly are experimentally studied. Factors modulating polymer to metal bonding including interfacial chemistry, surface contamination and material roughness are evaluated.

In power electronic, ceramic substrates are used owing to their high thermal conductivity and dielectric strength. These substrates cannot withstand high voltages in the range of 20kV because thickness limitations inherit from the direct bond copper manufacturing method. This manufacturing process uses high temperature in order to bond the material layers. This negatively affects the material’s reliability due to the differing materials thermal expansion coefficients and the resulting residual stress. All this results in hindering the ceramic substrate in obtaining a higher dielectric strength. In contrast, cold gas spray has the potential to provide higher reliability due to its bonding mechanism, which relies on plastic deformation of solid particles at very high strain rates during impact to create a mechanical bond, forming a thick deposit. However, cold gas spray on ceramics has not been widely studied due to their brittleness and their inability to form a metallic bond. This work is aimed at providing an effective processing parameter map of the cold gas spray process to achieve a thick copper deposit on aluminum nitride on the basis of the comparison of experimental results with a numerical model and finite element simulation formulated in Mathematica and ABAQUS, respectively.

Creep response of joints bonded with single-layered pressure sensitive adhesives (PSAs) was investigated in this study. PSAs are becoming more and more popular in the electronic industry as bonding media because of their ease of design, fast accurate bonding, environmentally-friendly bonding and ease of reworking. Such adhesive bonds are expected to experience complex, sustained loading conditions in service; e.g. loading due to large mass components, shock, temperature, or alignment mismatch of substrates. Stress-strain behavior of PSA bonding assembly has been extensively studied through experiments and simulations, including the effects of loading conditions (loading rate and temperature), PSA configurations (thickness of adhesive and single/double-layered PSAs), and bonding substrate surface properties (substrate material and surface roughness). However, the literature regarding the creep response of PSA-bonded assemblies is lacking and there is no literature on modeling methodologies for the creep response of such bonding systems. Similar to the stress-strain behavior of PSA-bonded assemblies, the creep response includes transitions between multiple hardening and softening phases. Experimental results indicate that the secondary creep rate can change by up to two orders of magnitude after each transition, which is too significant to ignore when estimating the creep deformation of joints bonded with this material system. The number of transitions is related to the configuration of the PSA system, i.e. the single-layered PSA has one transition while double-layers PSAs may have multiple transitions due to the additional interface(s) introduced by the carrier layer. This unique secondary creep behavior comes from the competition between hydrostatic stress relaxation and strain hardening, caused by cavitation and fibrillation processes, respectively. The total stress applied on the joint is equal to the summation of deviatoric stress and hydrostatic stress. An advanced model based on the stress-strain ‘block’ model [5–7] is developed for evaluating the creep response. This model has the capability to control the initiation and growth of cavities in the bulk of the PSA and at the interface between PSA and substrate. This model is able to capture the nonlinear visco-plastic behavior of the PSA fibrils and estimate the effects of flexible carrier layer on the transitions in creep curves. The model prediction shows reasonable agreement with experimental results in terms of the characteristic features in creep strain histories.

This work presents the design and characterization of a two-phase, embedded manifold-microchannel (MMC) system for cooling of high heat flux electronics. The study uses a thin-Film Evaporation and Enhanced fluid Delivery System (FEEDS) MMC cooler for high heat flux cooling of electronics. The work builds upon our group’s earlier work in this area with a particular focus on the use of an improved bonding structure and implementation of uniform heat flux heaters that collectively contribute to enhanced performance of the system. In many MMC systems targeted for high heat flux applications microchannels and manifolds are fabricated separately due to different dimensions and tolerances required for each. However, assembly of the system often leaves a gap between the channels and the manifold, thus causing the working fluid to leak through the top of the microfins leading to decreased cooler performance. The effect of this gap is parametrized and analyzed with ANSYS Fluent CFD simulations and discussed in this paper. The findings show that even a few microns wide gap can cause a noticeable degradation of the MMC system performance. Imperfect assembly and the deformation of a microchannel chip due to working fluid pressure can cause gaps, indicating the necessity of uniform and hermetic bonding between the manifold and the tips of the microfins. Furthermore, this work presents the need for better heater designs to enable uniform and high heat flux to the heat transfer surface. Serpentine heaters are often used to mimic electronics in a laboratory environment, but there is a lack of study on the performance characterization of the heaters themselves. In the current work, the performance of a conventional serpentine heater is characterized using ANSYS thermo-electric modeling software. The results show that conventional serpentine heaters are insufficient at providing uniform heat flux in applications where there is a lack of heat spreading-such as in the current embedded cooler — showing deviations ranging over 200 % of the nominal value. The deviations are caused by the many bends present in a serpentine pattern where current density concentrations vary significantly. Two alternate designs are proposed, and numerical simulations show that these new heater designs are capable of providing uniform heat flux, not deviating more than 20% from the nominal heat flux value. The conventional and newly proposed heaters are fabricated, tested, and analyzed with a working FEEDS system.

Wide bandgap (WBG) semiconductors are revolutionizing the world of power electronics. They have the potential to bring about an unprecedented increase in power density. The ability to switch at ultrafast rates, coupled with the promise of high temperature operation, make these devices extremely desirable. However, having superior semiconductor devices will not automatically translate to superior package characteristics. In real applications, the performance of a power device is only as good as the package allows. One of the major drawbacks plaguing contemporary power modules is the wire-bonded interconnection. Wire bonds offer a high parasitic inductance. This paper presents a novel wire bondless SiC power MOSFET packaging technique. A commercially available bare die was reconfigured into a chip-scale package. The new form factor enabled the MOSFET to be bonded to a patterned FR4 substrate using flip-chip bonding. The electrical interconnection between the package and the substrate was established using solder balls — thus eliminating the requirement for wire bonds. The motivation for using a wire bondless method was a reduction in stray parasitic inductances and an increase in the thermo-mechanical reliability. Lower parasitic inductances will facilitate high switching frequencies which will promote miniaturization, a reduction in electromagnetic interference (EMI), and lead to lower switching losses. The proposed approach was demonstrated to reduce the parasitic loop inductance by a fctor of > 3× as compared with wire bonded modules.

Silver is a leading competitor to gold and copper in fine pitch wire bonding used in the interconnection of microelectronic devices. Primary material for wire bonding has been gold, which gave way to copper in order for original equipment manufacturers to realize cost benefits. However, copper wire bonding has exhibited several reliability issues, especially in industrial and high temperature applications. Corrosion is the major problem, which was mitigated by coating the wire with palladium, which increased overall cost of production. Other concerns include harder free air ball (FAB) leading to under pad metallization cracking, smaller process window, excessive aluminum splash especially in fine pitch bonding, and lower throughput and yield arising from the hardness and stiffness of copper. Due to the above concerns, automotive, military and aerospace industries are still reluctant to fully adopt copper wire bonding. Light emitting diodes (LEDs) are also not manufactured with copper wires due to its low reflectance. Some of these industries are still using gold wire bonds in most of their packages, but are continually looking for an alternative. Silver wire bonds have good electrical and thermal conductivity, are less prone to corrosion than copper, have low melting points and comparable hardness to gold. Also, cost of silver has been shown to be similar to that of palladium coated copper wire, hence making it a good alternative. Silver wire bonding, a relatively new area of research, has attracted a lot of research focused on wire dopant material, bonding process, quality and reliability. This paper is aimed to serve as a comprehensive review of research done in this area, by summarizing the literature on silver wire bonding, establishing benefits and drawbacks over other wire bond materials and indicating reliability concerns along with failure modes and mechanisms.

Transition of ground vehicles to HEV and FEV has necessitated the operation of electronics in automotive underhood at high voltage bias and high temperature for extended period-of-time. Examples include gate drivers and IGBT modules. A typical automotive benchmark is operation for 10 years and 100,000 miles. Simultaneously, the first-level interconnects are migrating to use copper-wire interconnects in place of the previously used gold wire. Copper wire has higher propensity for corrosion and a narrower process-bonding window in comparison with gold wire based systems. Exposure to high temperature, humidity and bias influences the mobility of ions in the EMC and thus the contaminant transport to the WB interfaces. Measurements of diffusion behavior of EMCs at high temperature and high voltage bias are not available for readily being used in models. Prior studies have focused on biased humidity tests on wire bonds with the amplitude of the bias being limited up to 3.5Volts. In this paper, a PWM-controlled-gate drive-based test setup is established to study the effect of high voltage (up to 20Volts) on Cu-Al wire bond interconnects. A migration-diffusion cell experiment is designed to quantify the effect of voltage bias on transport of chlorine in EMCs. Diffusion coefficient and ionic mobility of chlorine at different temperatures are obtained. Resistance spectroscopy measurements show the progression of corrosion induced by voltage bias. A corrosion simulation is used to quantify the effect of voltage bias on corrosion rate of Cu-Al wire bond.

We present the operation of capacitive micromachined ultrasonic transducers (CMUTs) in permanent contact mode as an efficient transducer. The gap height of our transducers is chosen to be slightly smaller than the static deflection of the plate due to the pressure difference between the ambient and the vacuum cavity. Thus, the plates are in contact with the bottom of the cavities even with no dc bias applied. The devices were fabricated based on the thick box process. High-temperature assisted direct wafer bonding technique was used to fabricate devices with such large cell size (radii ∼ 2000 μm) featuring low frequencies ∼100–150 kHz. Extensive acoustic characterization was performed to demonstrate the behavior of such CMUTs in terms of displacement profile, output pressure and acoustic pitch-catch response. A maximum sound pressure of ∼145 dB (SPL) at the transducer surface is measured at 240 V dc and 10 V ac with 100 cycles of burst signal. This is a great improvement from conventional CMUTs (with deeper gap height, operating at 55 kHz), which requires 350 V dc and 200 V ac in order to achieve an output pressure of 129 dB (SPL) at the transducer surface. The results presented in this paper demonstrate that operating CMUTs in permanent contact mode indeed enhances the device output pressure, and provides a good candidate for efficient ultrasonic transducers.

Ultrasound is increasingly in demand as a medical imaging tool and can be particularly beneficial in the field of intracardiac echocardiography (ICE). However, many challenges remain in the development of a 3D ultrasound imaging system. We have designed and fabricated a quad-ring capacitive micromachined ultrasound transducer (CMUT) for real-time, volumetric medical imaging. Each CMUT array is composed of four concentric, independent ring arrays, each operating at a different frequency, with 128 elements per ring. In this project, one ring will be used for imaging. A large (5mm diameter) lumen is available for delivering other devices, including high intensity focused ultrasound transducers for therapeutic applications or optical fibers for photoacoustic imaging. We address several challenges in developing a 3D imaging system. Through wafer vias are incorporated in the fabrication process for producing 2D CMUT arrays. Device integration with electronics is achieved through solder bumping the arrays, designing a flexible PCB, and flip chip bonding CMUT and ASICs to the flexible substrate. Finally, we describe a method for integrating the flex assembly into a catheter shaft. The package, once assembled, will be used for in-vivo open chest experiments.

Due to its superior mechanical and electrical properties, as well as low cost, Cu is gradually replacing Au as wire bonding material. However, since copper is a stiffer material, it requires greater bonding force, which in turn increases risk of bond pad cratering and inter-layer dielectric (ILD) fracture. A critical challenge to numerically modeling the pad cratering or ILD fracture is the availability of appropriate constitutive models for the Cu free-air balls (FAB). In this work we first present rate and temperature dependent force-displacement response of micron-sized Cu FAB characterized using a custom-built high-precision microtester. From the experimental force-displacement data, Anand viscoplastic constitutive model parameters are obtained using an inverse finite element analysis procedure, where the material parameters are iterated through an automated procedure until the finite element and experimental force-displacement responses match. The constitutive model parameters to describe the FAB behavior at low and intermediate strain rates and at high temperatures are obtained and reported in this paper.

Recent electronic device packaging, for instance, CSP has a bonded structure of IC chip and polymers, and delamination occurs frequently at the interface between IC and a resin. Furthermore, thermal stresses which are caused by a temperature variation in the bonding process of CSP and heat cycles for environment temperature will influence on the strength of interface. In the present paper, the delamination test for specimens with different thicknesses of an interlayer is carried out to investigate the strength of multi-layered joints, and the critical value for the intensity of singularity at delamination of interface is determined through a numerical analysis using a boundary element analysis. In experiment, a silicon wafer is joined with a silicon-on-sapphire (SOS) plate by a resin. The SOS is composed of silicon film and sapphire plate. The joining strength in silicon, resin and SOS joints with a rectangular bonding area is investigated. The bonded specimens are prepared under different cooling rate. Load is applied to the specimen so as to delaminate at the interfaces of silicon film and sapphire. Delamination occurs at the interface between silicon film and sapphire plate in the specimen. Nominal stress for delamination is about 2.23–3.59 MPa. From a comparison of the strength of joint for rapid and slow cooling conditions, it is found that the residual stress reduces the strength of joint. In the numerical analysis, the intensity of singularity at the corner of interface for a unit load is determined. The intensity of singularity at the corner of the interface is related to the intensities of singularity in the radial direction and on the angle from the side free surface. The critical intensity of singularity for delamination of the interface is obtained by multiplying the force at delamination. Then, the critical intensity of singularity is determined as 168 MPa•mm 0.18 regardless of the thickness of silicon film.

Despite being a critical phenomenon of tremendous technological significance in ultrasonic flip-chip and wire bonding processes of today’s microelectronic devices, interfacial bond formation still calls for better understanding at a fundamental level. The goal of the research is to improve these processes through better understanding and modeling of bond formation. This paper presents a micromechanics model that addresses increasing contact area during ultrasonic cyclic loading cycle. The micromechanics model provides interfacial shear stress as boundary condition to FEM simulations of ultrasonic bonding processes. Comparison between preliminary results and experimental data is conducted.

Solid liquid inter diffusion (SLID) is an interconnection technique for electronic packaging, particularly beneficial for high power and harsh environments conditions. It consists of the bonding of two materials with different melting points at a low processing temperature to achieve a high melting point interconnection. The materials investigated in this work are a gold-tin bond attaching a SiC diode to an AlN direct-bond-copper (DBC) substrate. Gold (Au) is the high melting point constituent while the eutectic gold-tin (80 wt.% Au-20 wt.%Sn) offers the low melting point (280°C). This work is aimed at the microstructural evaluation of the joints at different bonding and aging conditions in an effort to get the insights of this interconnection technology from a metallurgical perspective. Four different bonding conditions were used: 315°C-5min, 315°C-10min, 340°C-1min and 340°C-5min; from which a base-line as built condition was assessed by means of metallographical analysis. Furthermore, the samples were aged at 250°C from 1000 to 4000 hours in increments of 1000hrs to study and quantify the microstructural stability and intermetallic (IMC) growth at the interface. This aging experiment has been designed to obtain accelerated information on the kinetics of this reaction so that predictive models can be developed for the real application conditions. The samples were diced, polished and analyzed following standard metallographical techniques; both optical and electronic microscopy (SEM-EDS) was employed. The as-built samples, for the four bonding conditions, presented differences in IMC growth with the thickest layers appearing at the harshest processing conditions. After aging the IMC kept growing and the formation of a new IMC layer was discovered and investigated, furthermore, cracks started to show in some of the samples. It was observed that after 4000 hours some of the cracks extended across the whole interface.

The focus of this paper is on the stress-strain behavior and creep response of a pressure-sensitive adhesive (PSA) with and without carrier layers. This study consists of two phases. The first phase focuses on understanding of the effects of fabrication profiles, including bonding pressure, bonding temperature, bonding time, and aging time, on the PSA joint strength. This part of the study is used to identify an acceptable bonding and aging conditions for manufacturing a robust PSA bonded assembly. Specimens fabricated with this selected set of bonding process conditions are then used for mechanical characterization. The second phase focuses on the assembly’s mechanical behavior (stress-strain behavior and the creep curves) under different loading conditions, including loading stress, loading rate, and loading temperature. The mechanical behavior of PSA bonded assemblies is affected not only by the loading conditions, but also by the assembly architecture. The mechanical behaviors and failure modes of PSAs with and without carrier layers are compared. The reasons for these differences are also discussed.

During ultrasonic ball bonding of copper wire to aluminum pad, the two alloys are joined over an immensely short period of time (<100ms), at a relatively low temperature (< 200°C). Bond formation in such condition is related to accelerated diffusional processes and formation of intermetallic compounds (IMC). Despite the industrial importance of the phenomenon, the micro-mechanism of IMC formation is not clearly understood, nor deeply studied. One of the main barriers toward understanding the phenomena is the limited capability of experimental analysis for analyzing processes occurring over short period of time. In this research, a combination of theoretical analysis and finite element simulation is used to investigate the mechanisms that lead to diffusion enhancement and, as a result, IMCs formation.

Three-dimensional (3D) packaging technology is directly related to the increasing I/O number as stacking chips. This technology has the potential to produce integrated circuits with a much better combination of cost, functionality, performance and power consumption. However, stacked chips raise several thermal issues that need to be addressed and eliminated. In this study, a quantitative study of the conventional solder-based interconnection is conducted based on many different cases of thermal loading, using finite element analysis (FEA). This preliminary study clearly shows limitation of the solder-based interconnection in the thermal management perspective. Underfill for microbμmp acts as a barrier of heat transfer in the conventional 3D stacked chip packages. Therefore, as an alternative, Cu-to-Cu direct bonding (CuDB), which has a better thermal conductivity, is proposed. Its parametric study is performed under the same/different loading conditions and dimensions. This study helps to highlight the thermal behavior of 3D packages consisting of various interconnections. Finally, based on the results, we can propose qualitative design guidelines of 3D packaging depending on various environment and conditions.

Cadmium plated circular connectors and chromate conversion coated aluminum chassis are widely used on electronic equipment for both civilian and military aerospace applications. This article discusses electrical bonding resistance problems associated with cadmium plated circular connectors and chromate conversion coated aluminum chassis and proposes an innovative way to solve that problem.

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.

There is an urgent need in surface mount technology (SMT) for a nontoxic, reusable and low temperature bonding technique which can afford good mechanical support as well as electrical contact. Meanwhile in the nanotechnology, many excellent and unique structure-related properties such as the high mechanical strength, the high conductivity and the adhesion ability of gecko feet have been studied. Our lab proposes a new patterned structure of Au nanowire array named nanowire surface fastener (NSF), which cold bonding for surface mount technology can be realized at room temperature. Then various methods have been developed to fabricate nanowire, such as arc discharge, catalytic CVD growth and template synthesis, and so on. Among these methods, the template method has been widely used for preparing one-dimensional nanostructures such as metals, semiconductors, polymers, and other materials by electrochemical, electroless deposition or sol-gel technique. Especially anodic aluminum oxide template assisted way has attached considerable attention due to its unique structure properties, such as controllable pore diameter, extremely narrow pore size distribution with high densities, high aspect ratios, and ideally cylindrical pore shape. The well arranged porous anodic aluminum oxide membrane is fabricated from aluminum film by two steps zM oxalic acid electrolytes. The anodic aluminum oxide membrane was investigated for features such as pore size, interpore distance, and thickness by 40 V. It is important for fabrication of porous anodic aluminum oxide template to find out elimination of the barrier layer of oxide and the pore extending rate by 0.5 M phosphoric acid. Morphologies of surface of aluminum film between anodization process and the anodic aluminum oxide barrier layer was researched by using atomic force microscope and scanning electron microscope. Results showed that the anodic aluminum oxide having the same diameter of the pore and the well arranged pore array without branching channel was obtained. The diameter of the pore before the pore extending treatment is 42 nm and the diameter of the pore after the pore extending treatment for 30 minutes is 86 nm. It was found that the diameter of the pore increased per 15 nm by the pore extending treatment for 10 minutes. We fabricated the through-hole anodic aluminum oxide template and made Cu nanowire by the template of our own making. By using Cu nanowire, we try to produce nanowire surface fastener and evaluate its properties.

Portable electronics devices such as mobile phone and portable music player become compact and improve their performance. High-density packaging technology such as CSP (Chip Size Package) and Stacked-CSP is used for improving the performance of devices. CSP has a bonded structure composed of materials with different properties. A mismatch of material properties may cause stress singularity, which lead to the failure of bonding part in structures. In the present study, a strain singular field near inter-face edge in three-dimensional joints is investigated using digital image correlation method. A specimen which silicon chip was embedded in resin is used in experiment and tensile load is applied to the specimen. Photograph of specimen surface is taken before and after loadings by laser microscope. Displacement on the surface was evaluated by the digital image correlation method (DICM) using data of surface pattern on the specimen, which the cross correlation coefficients for surface pattern are maximized. Strain on surface of specimen is calculated by using the moving least square method. On the other hand, 3D element free Galerkin method is applied to compute the displacement and strain distribution in a three-dimensional model of the specimen. In the element free Galerkin method, the physical values, i.e., displacement, strain and stress, can be obtained by using the displacement data at node. In this research, strain distribution near the edge of interface is computed based on the element free Galerkin method. Finally, the strain distribution obtained by the digital image correlation method and the moving least square method is compared with that obtained by the element free Galerkin method. The intensity of strain singularity is determined numerically and experimentally.