Abstract
Electronic components designed for commercial purposes are subjected to high G shock loads and thermo-mechanical loads in defense and aerospace applications, making reliability a crucial factor in these harsh environments. To improve the reliability of printed circuit boards in such applications, they are potted, but interfacial delamination at the potting/PCB interface remains a major failure mode. The interfacial properties of the potting/PCB interface evolve over time with sustained exposure to high temperatures, which makes it necessary to investigate the effects of such exposure on the interface properties. The present study focuses on investigating the evolution of interfacial properties at the potting/PCB interface with respect to high-temperature exposure and the use of restraint mechanisms. A circular printed circuit board with fine-pitch electronic packages and multilayer ceramic chip capacitors is assembled, and bimaterial specimens of potting/PCB are made to investigate the evolution of interfacial properties. The specimens are tested under four-point bend loading, and the interfacial fracture toughness properties and cohesive zone parameters are determined for each of the interfaces. Additionally, potted circular printed circuit boards with four different potting materials are tested for pristine and 90-day aging at 150°C. The boards are subjected to shock levels of 10,000g and 25,000g to evaluate the efficacy of the potting compounds on the solder joint reliability of fine-pitch electronics and large discrete components. The study investigates an aspect of potting electronics that has not been reported earlier and could have practical implications for manufacturers. The cohesive zone parameters obtained from the bi-material samples are validated and used to develop a predictive finite element high G shock model for the circular board assemblies. The experimental test conditions are validated with the predictive model output to provide a better understanding of the interfacial properties of the potting/PCB interface. The study also discusses the potential use of the predictive model in the design of electronic components for harsh environmental applications. In summary, the study investigates the evolution of interfacial properties at the potting/PCB interface with respect to high-temperature exposure and the use of restraint mechanisms. The study also evaluates the efficacy of different potting compounds on the solder joint reliability of fine-pitch electronics and large discrete components for various aging durations. The cohesive zone parameters obtained from the bi-material samples are validated and used in the development of a predictive finite element high G shock model. The study could have practical implications for manufacturers designing electronic components for harsh environmental applications, and it provides valuable insights into the interfacial properties of the potting/PCB interface.
