In recent years, semiconductor products have developed rapidly, from desktop computers with basic computing to Internet-connected smartphones, to emerging intelligent and perceived smart system products, such as mass-produced of smart home appliances, smart watches, and under development of smart glasses. The product trend is toward high performance, multi-functional integration, thinner profile and lower cost features. These requirements are interrelated with wafer technology and assembly process development. The advanced wafer technology, such as 5nm / 3nm, will provide higher performance. However, as Moore’s Law is approaching the physical limit, the industry has turned to the development of advanced packaging solution technologies to break through this bottleneck. At present, the industry’s forward-looking packaging platform includes 2.5 D, 3D, Fan-out and SiP modules, etc., which technologies can integrate chiplet, chip stack, passive components as heterogeneous integrated packaging solutions.
Fan-Out MCM Platform has integrative characteristics for homogeneous / heterogeneous wafers and passives, lower cost and lower profile advantage than 2.5D, also provided comparable performance to 2.5D by proper RDL / Substrate layout design. In addition, in order to meet the high-performance characteristics of products, toward developing multi-layer RDL layers (more than 3 layers). This article will plan a series of multi-RDL layers sample tests, RDL sample build of line width/line space of 1/1um and introduce the related process challenge, microstructure data.