Wafer Level Chip Scale Package (WLCSP) has been a favorable packaging solution for compact portable consumer electronics. The microelectronics industry introduced Extra Low K (ELK) to enhance electric performances with the cost of diminishing mechanical reliability. The ELK itself and its interfaces are highly fragile and susceptible to fracture. ELK cracking under bumps and ELK inter layer delamination (ILD) from die corners are often observed during and after solder reflow and qualification process such as accelerated thermal cycling (ATC). In this study, the underfill selection and its fillet formation influence to the Chip Packaging Interactions (CPI) of WLCSP was investigated through an experimental technique and numerical analysis. For the experimental assessment, thermo-mechanical interactions between die corner and underfill was investigated. Digital image correlation (DIC) technique with optical microscope was utilized to quantify the deformation behavior and strains of cross-sectioned WLCSP die corner subjected to thermal loading from 25°C to 125°C. The results clearly show captured deformations of die corner area under thermal loading. For the fillet formation influence, it shows that the high underfill fillet configuration gives higher normal strain at the die corner area during thermal cycling. For the underfill selection, it clearly shows that the strain difference at corner solder during thermal cycling caused by two different type of underfill material. Finally, finite element analysis (FEA) was conducted by simulating the thermal loading applied in the experiments and validated with experimental results. Then, using the FEA analysis, parametric study for underfill material properties and fillet height were performed on the ELK reliability of WLCSP. Energy release rate of the die corner crack were obtained and used as damage indicators for die corner ELK delamination.
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ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems
August 27–30, 2018
San Francisco, California, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
978-0-7918-5192-0
PROCEEDINGS PAPER
Quantification of Underfill Influence to Chip Packaging Interactions of WLCSP
Huayan Wang,
Huayan Wang
Binghamton University, Vestal, NY
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Vanlai Pham,
Vanlai Pham
Binghamton University, Vestal, NY
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Panju Shang,
Panju Shang
Huawei Technology Co., Ltd., Shenzhen, China
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Cheng Zhong,
Cheng Zhong
Huawei Technology Co., Ltd., Shenzhen, China
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Seungbae Park
Seungbae Park
Binghamton University, Vestal, NY
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Huayan Wang
Binghamton University, Vestal, NY
Shuai Shao
Binghamton University, Vestal, NY
Vanlai Pham
Binghamton University, Vestal, NY
Panju Shang
Huawei Technology Co., Ltd., Shenzhen, China
Cheng Zhong
Huawei Technology Co., Ltd., Shenzhen, China
Seungbae Park
Binghamton University, Vestal, NY
Paper No:
IPACK2018-8257, V001T01A004; 7 pages
Published Online:
November 13, 2018
Citation
Wang, H, Shao, S, Pham, V, Shang, P, Zhong, C, & Park, S. "Quantification of Underfill Influence to Chip Packaging Interactions of WLCSP." Proceedings of the ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. San Francisco, California, USA. August 27–30, 2018. V001T01A004. ASME. https://doi.org/10.1115/IPACK2018-8257
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