3D packaging technology and TSV (Through Silicon Via) technology have been developed to reduce size and improve performance of semiconductor devices. On the other hand, cooling performance is decreased because thermal sources are accumulated and concentrated by chip stacking. In particular, unsteady thermal loads by hot spot, which is steep temperature elevation within a local area, produce damage in stacked semiconductor chips. In this study, temperature elevation in stacked chips and stresses around TSV structure in 3D SiP (Three Dimensional System in Package) are discussed with a large scale and a parallel computing simulator, which was based on FEM (Finite Element Method), under unsteady thermal conditions as hot spot. The level of heat generation was varied and conditions for device operation were suggested. In addition, stresses of Cu-TSV and Si chips are discussed as function of level of heat generation by hot spot to ensure the reliability of 3D SiP.
- Electronic and Photonic Packaging Division
Thermal Stress Simulation for 3D SiP With TSV Structure Under Unsteady Thermal Loads
Kinoshita, T, Kawakami, T, Sugiura, T, Matsumoto, K, Kohara, S, & Orii, Y. "Thermal Stress Simulation for 3D SiP With TSV Structure Under Unsteady Thermal Loads." Proceedings of the ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. Volume 2: Advanced Electronics and Photonics, Packaging Materials and Processing; Advanced Electronics and Photonics: Packaging, Interconnect and Reliability; Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales. San Francisco, California, USA. July 6–9, 2015. V002T02A020. ASME. https://doi.org/10.1115/IPACK2015-48142
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