The electronic hardware miniaturization trend continues unabated. The reduced feature spacing expose the high voltage power supply circuits to arcing. The power MOSFET gate to drain and the drain to source lead gaps are narrow enough for zinc whiskers emanating from under the raised floor zinc plated tiles to arc across the MOSFET leads. Arcing can also occur because of paper cellulose fibers and dust in high relative humidity environments. The physics of arcing will be presented. Paschen’s law of arcing will be described; it will be shown how the law led to a novel way of testing power supplies for propensity to arcing. Examples of application of the test, called the partial vacuum test, to power supplies will be described. Testing the integrity of conformal coating is one useful application of the partial vacuum test. A novel zinc whisker spray test, developed to determine the spacing required to avoid arcing between features at high electric potential between them, will be described and its results will be presented that verify the UL feature spacing guidelines.
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ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels
July 6–9, 2015
San Francisco, California, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
978-0-7918-5689-5
PROCEEDINGS PAPER
Arcing and Spacing Requirements for High Voltage Printed Circuit Boards
Prabjit Singh
Prabjit Singh
IBM Corporations, Poughkeepsie, NY
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Prabjit Singh
IBM Corporations, Poughkeepsie, NY
Paper No:
IPACK2015-48180, V002T02A011; 7 pages
Published Online:
November 19, 2015
Citation
Singh, P. "Arcing and Spacing Requirements for High Voltage Printed Circuit Boards." Proceedings of the ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. Volume 2: Advanced Electronics and Photonics, Packaging Materials and Processing; Advanced Electronics and Photonics: Packaging, Interconnect and Reliability; Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales. San Francisco, California, USA. July 6–9, 2015. V002T02A011. ASME. https://doi.org/10.1115/IPACK2015-48180
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