During the fabrications of 2.5D and 3D advanced packages, the needs for intermediate thinning and planarization processes persistently exit. This paper highlights the attributes of successful implementations, i.e., increased performances and yields for these processes, which have been identified by the market requirements for a variety of applications. Different packages with different materials systems and product goals lead to different requirements. This paper includes the thinning and polishing of TSV wafers in bonded wafer pairs for Si IC devicess or interposers, the thinning of overmolded, reconstituted wafers in eWLB applications, and the planarizations of metal bumps and RDL features in PoP, CSP, or fine line-and-space (L/S) substrate fabrications.

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