During the fabrications of 2.5D and 3D advanced packages, the needs for intermediate thinning and planarization processes persistently exit. This paper highlights the attributes of successful implementations, i.e., increased performances and yields for these processes, which have been identified by the market requirements for a variety of applications. Different packages with different materials systems and product goals lead to different requirements. This paper includes the thinning and polishing of TSV wafers in bonded wafer pairs for Si IC devicess or interposers, the thinning of overmolded, reconstituted wafers in eWLB applications, and the planarizations of metal bumps and RDL features in PoP, CSP, or fine line-and-space (L/S) substrate fabrications.
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ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels
July 6–9, 2015
San Francisco, California, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
978-0-7918-5689-5
PROCEEDINGS PAPER
Attributes of Advanced Thinning and Planarization Processes in 2.5D and 3D Packaging Recognized by Market Demands
Frank Wei
Frank Wei
DISCO Corporation, Tokyo, Japan
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Frank Wei
DISCO Corporation, Tokyo, Japan
Paper No:
IPACK2015-48387, V002T02A007; 5 pages
Published Online:
November 19, 2015
Citation
Wei, F. "Attributes of Advanced Thinning and Planarization Processes in 2.5D and 3D Packaging Recognized by Market Demands." Proceedings of the ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. Volume 2: Advanced Electronics and Photonics, Packaging Materials and Processing; Advanced Electronics and Photonics: Packaging, Interconnect and Reliability; Fundamentals of Thermal and Fluid Transport in Nano, Micro, and Mini Scales. San Francisco, California, USA. July 6–9, 2015. V002T02A007. ASME. https://doi.org/10.1115/IPACK2015-48387
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