The thermal network method has a long history with thermal design of electronic equipment. In particular, a one-dimensional thermal network is useful to know the temperature and heat transfer rate along each heat transfer path. It also saves computation time and/or computation resources to obtain target temperature. However, unlike three-dimensional thermal simulation with fine pitch grids and a three-dimensional thermal network with sufficient numbers of nodes, a traditional one-dimensional thermal network cannot predict the temperature of a microprocessor silicon die hot spot with sufficient accuracy in a three-dimensional domain analysis. Therefore, this paper introduces a one-dimensional thermal network with average temperature nodes. Thermal resistance values need to be obtained to calculate target temperature in a thermal network. For this purpose, thermal resistance calculation methodology with simplified boundary conditions, which calculates thermal resistance values from an analytical solution, is also introduced in this paper. The effectiveness of the methodology is explored with a simple model of the microprocessor system. The calculated result by the methodology is compared to a three-dimensional heat conduction simulation result. It is found that the introduced technique matches the three-dimensional heat conduction simulation result well.
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ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels
July 6–9, 2015
San Francisco, California, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
978-0-7918-5688-8
PROCEEDINGS PAPER
Microprocessor Silicon Die Temperature Prediction by Simplified Boundary Conditions Available to Purchase
Tomoyuki Hatakeyama,
Tomoyuki Hatakeyama
Toyama Prefectural University, Imizu-Shi, Toyama, Japan
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Shinji Nakagawa,
Shinji Nakagawa
Toyama Prefectural University, Imizu-Shi, Toyama, Japan
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Masaru Ishizuka
Masaru Ishizuka
Toyama Prefectural University, Imizu-Shi, Toyama, Japan
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Koji Nishi
AMD Japan Ltd., Tokyo, Japan
Tomoyuki Hatakeyama
Toyama Prefectural University, Imizu-Shi, Toyama, Japan
Shinji Nakagawa
Toyama Prefectural University, Imizu-Shi, Toyama, Japan
Masaru Ishizuka
Toyama Prefectural University, Imizu-Shi, Toyama, Japan
Paper No:
IPACK2015-48205, V001T09A082; 8 pages
Published Online:
November 19, 2015
Citation
Nishi, K, Hatakeyama, T, Nakagawa, S, & Ishizuka, M. "Microprocessor Silicon Die Temperature Prediction by Simplified Boundary Conditions." Proceedings of the ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. Volume 1: Thermal Management. San Francisco, California, USA. July 6–9, 2015. V001T09A082. ASME. https://doi.org/10.1115/IPACK2015-48205
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