As thermal management techniques for 3D chip stacks and other high power density electronic packages continue to evolve, interest in the thermal pathways across substrates containing a multitude of conductive vias has increased. To facilitate the use of numerical models that can reduce computational costs and time in the thermal analysis of through-layer via (TXV) structures, much research to date has focused on defining effective anisotropic thermal properties for a pseudo-homogeneous TXV medium using isothermal boundary conditions. While such an approach eliminates the need to model heat flow through individual vias, the resulting properties can be shown to depend on the specific boundary conditions applied to a unit TXV cell. More specifically, effective properties based on isothermal boundary conditions fail to capture the local “micro-spreading” resistance associated with more realistic heat flux distributions and local hot spots on the surface of these substrates.
This work assesses how the thermal spreading resistance present in arrays of vias in interposers, substrates, and other package components can be properly incorporated into the modeling of these arrays. We present the conditions under which spreading resistance plays a major role in determining the thermal characteristics of a via array and propose methods by which designers can both account for the effects of spreading resistance and mitigate its contribution to the overall thermal behavior of such substrate-via systems. Finite element modeling of TXV unit cells is performed using commercial simulation software (ANSYS).
Compactly stated, micro-spreading contributes to the total resistance RT = R1d + (fu + fl)Rsp,max, where 0≤ f ≤ 1 are adjustment factors that depend on the conditions at the upper and lower surfaces of the via array layer and Rsp,max occurs under worst-case conditions.