In this paper, we present the experimental characterization of 3D packages using a dedicated stackable test chip. An advanced CMOS test chip with programmable power distribution has been designed, fabricated, stacked and packaged in molded and bare die 3D packages. The packages have been experimentally characterized in test sockets with and without cooling, and soldered to the PCB. Using uniform and localized hot spot power distribution, the thermal self-heating and thermal coupling resistance and the lateral spreading in the 3D packages have been studied. Furthermore, the measurements have been used to characterize the thermal properties of the epoxy mold compound and the die-die interface and to calibrate a thermal model for the calculation of equivalent properties of underfilled μbump arrays. This model has been applied to study the trade-off between the stand-off height reduction and the underfill thermal conductivity increase in order to reduce the inter die thermal resistance.
- Electronic and Photonic Packaging Division
Experimental Characterization of the Vertical and Lateral Heat Transfer in 3D-SIC Packages
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Oprins, H, Cherman, V, Van der Plas, G, De Vos, J, & Beyne, E. "Experimental Characterization of the Vertical and Lateral Heat Transfer in 3D-SIC Packages." Proceedings of the ASME 2015 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2015 13th International Conference on Nanochannels, Microchannels, and Minichannels. Volume 1: Thermal Management. San Francisco, California, USA. July 6–9, 2015. V001T09A068. ASME. https://doi.org/10.1115/IPACK2015-48316
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