Compact Thermal Modeling Methodology for Active and Thermal Bumps in 3D Microelectronic Packages

Accurate estimation of the thermal conductivity of logic-memory and memory-memory interfaces, between stacked die in 3D microelectronic packages, is key to effective design and early estimates of performance and reliability. Typically, interconnect layers contain hundreds to a few thousands of bumps. Hence lumped/compact modeling of this interfacial layer is essential to reduce computational time and complexity. The typical approach to this lumped modeling is to estimate the effective conductivity of the layer by assuming the bumps and underfill regions can be modelled as parallel thermal resistances (referred to as the volumetric method). This work demonstrates that the volumetric method can significantly underpredict 3D stack thermal resistance and junction temperatures. An alternative method-referred to as the single bump method-of estimation of the thermal conductivity of interconnect layers in 3D stacked-die packages is presented. Studies demonstrate that the proposed single bump method captures the heat transfer in these interfaces accurately. Validation of the single bump modeling is presented by comparing the single bump and volumetric methods with fully discretized models. This comparison also demonstrates that the prevalent volumetric method overestimates the effective thermal conductivity of the interface, while the single bump approach results in more accurate assessment of 3D stack resistance.