3D ICs with through-silicon vias (TSVs) can achieve high performance while exacerbating the problem of heat removal. This necessitates the use of more aggressive cooling solutions such as micropin-fin based fluidic cooling. However, micropin-fin cooling comes with overheads such as non-uniform cooling capacity along the flow direction and restriction on the position of TSVs to where pins exist. 3D gate and TSV placement approaches un-aware of these drawbacks may lead to detrimental effects and even infeasible chip design. In this paper, we present a hierarchical partitioning based algorithm for co-placing gates and TSVs to co-optimize the wire-length and in-layer temperature uniformity, given the logical level netlist and layer assignment of gates. Compared to the wire-length driven gate placement followed by a TSV legalization stage, our approach can achieve up to 75% and 25% reduction of in-layer temperature variation and peak temperature, respectively, with the cost of 13% increase in wire-length.

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