A sensor for detecting imperfections in the distribution of a dielectric thermal interface is proposed. The sensor can detect imperfections such as voids, cracks, and interface gap changes on the millimeter scale. A rake of long, parallel electrodes is imbedded flush into each opposing substrate face of a narrow gap interface, and exposed to the gap formed between the two surfaces. Electrodes are oriented such that their lengthwise dimension in one substrate runs perpendicular to the other. Capacitance measurements taken at each crossing point (junction) allow for characterization of the region, and subsequently, detection of voids present or changes in gap size. The electric field associated with each electrode junction is numerically simulated and analyzed. Design criteria for the electrode junctions that localize the electric fields are presented. The electrode configuration employed gives rise to a non-trivial network of interacting capacitances. Due to these interactions, the actual capacitance at any given junction cannot be measured directly; instead, the measurement represents an equivalent capacitance resulting from this network. A generalized solution for analyzing the circuit network is presented. An experimental test unit is described, and experimental data are presented for measurements from a typical electrode junction. The results agree with predictions from the network model for cases that meet the design criteria for electric field localization; when the localization criteria are not met, the measurements deviate from the model predictions as expected.
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ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems
July 16–18, 2013
Burlingame, California, USA
Conference Sponsors:
- Electronic and Photonic Packaging Division
ISBN:
978-0-7918-5576-8
PROCEEDINGS PAPER
A Capacitance-Based Technique for Characterization of Dielectric Interfaces Using a Grid of Electrode Junctions
Stephen H. Taylor,
Stephen H. Taylor
Purdue University, West Lafayette, IN
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Suresh V. Garimella
Suresh V. Garimella
Purdue University, West Lafayette, IN
Search for other works by this author on:
Stephen H. Taylor
Purdue University, West Lafayette, IN
Suresh V. Garimella
Purdue University, West Lafayette, IN
Paper No:
IPACK2013-73283, V002T08A051; 10 pages
Published Online:
January 20, 2014
Citation
Taylor, SH, & Garimella, SV. "A Capacitance-Based Technique for Characterization of Dielectric Interfaces Using a Grid of Electrode Junctions." Proceedings of the ASME 2013 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems. Volume 2: Thermal Management; Data Centers and Energy Efficient Electronic Systems. Burlingame, California, USA. July 16–18, 2013. V002T08A051. ASME. https://doi.org/10.1115/IPACK2013-73283
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