Residual Stress in Silicon Caused by Cu-Sn Wafer-Level Packaging

The level of stress in silicon as a result of applying Cu-Sn SLID wafer level bonding to hermetically encapsulate a high-performance infrared bolometer device was studied. Transistors are present in the read out integrated circuit (ROIC) of the device and some are located below the bond frame. Test vehicles were assembled using Cu-Sn SLID bonding and micro-Raman spectroscopy was applied on cross sectioned samples to measure stress in the silicon near the bond frame. The test vehicles contained cavities and the bulging of the structures was studied using white light interferometry. The test vehicles were thermally stressed to study possible effects of the treatments on the level of stress in the silicon. Finite element modeling was performed to support the understanding of the various observations. The measurements indicated levels of stress in the silicon that can affect transistors in regions up to 15 μm below the bond frame. The observed levels of stress corresponded well with the performed modeling. However, no noticeable effect was found for the ROIC used in this work. The specific technology used for the fabrication of the ROIC of a MEMS device is thus decisive. The level of stress did not appear to change as a result of the imposed thermal stress. The level of stress caused by the bond frame can be expected to stay constant throughout the lifetime of a device.