Three-dimensional (3D) chip stacking is a promising approach for high performance microsystems. Such vertical integration could increase the clock frequency and reduce the signal delay. During operation, the input signal and the resulting input power change with time. Realistic power maps on active chip tiers produce highly non-uniform heat flux patterns with hotspots, which change with time. In this paper, a transient compact model of a multi-layer chip stack subjected to time dependent power map was developed. Inter-tier single phase microfluidic cooling with a pin fin array was used to enhance heat transfer. The validity of the compact model was confirmed by comparison with full computational fluid dynamics/heat transfer (CFD/HT) modeling. It was found that the transient compact model ran thousand times faster than the CFD/HT model. The maximum deviation between the two models was 1 °C. The compact model was then used to analyze the transient thermal response of a 4 layer dual core stack of Penryn microprocessors when a total power of 172.4 W with a 300 W/cm2 hot spot was suddenly applied. The hotspot temperature rise approaches 35 °C, at a steady state time of about 0.015 s. The temperature rise of bottom tier was always higher than the other three tiers during the transient process because it has only single side cooling, while other tiers have double sided cooling. Also, different power maps and flow patterns, including parallel and counter flow for different layers were investigated. It was found that controlling the flow in different layers individually instead of applying the same flow conditions could achieve better thermal performance and energy savings.

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